[PATCH 06/16] arm64: dts: qcom: shikra: Add EPSS L3 interconnect provider node

[Komal Bajaj]

From: Raviteja Laggyshetty <raviteja.laggyshetty@xxxxxxxxxxxxxxxx>

Add Epoch Subsystem (EPSS) L3 interconnect provider node for Shikra SoC.

Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@xxxxxxxxxxxxxxxx>
Signed-off-by: Komal Bajaj <komal.bajaj@xxxxxxxxxxxxxxxx>
---
 arch/arm64/boot/dts/qcom/shikra.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 238772f064ec..ebdb4bc15d76 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -6,6 +6,7 @@
 #include <dt-bindings/clock/qcom,rpmcc.h>
 #include <dt-bindings/clock/qcom,shikra-gcc.h>
 #include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
 #include <dt-bindings/dma/qcom-gpi.h>
 #include <dt-bindings/interconnect/qcom,rpm-icc.h>
 #include <dt-bindings/interconnect/qcom,shikra.h>
@@ -1833,6 +1834,14 @@ frame@f42d000 {
 			};
 		};
 
+		epss_l3: interconnect@fd90000 {
+			compatible = "qcom,shikra-epss-l3";
+			reg = <0x0 0x0fd90000 0x0 0x1000>;
+			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
+			clock-names = "xo", "alternate";
+			#interconnect-cells = <1>;
+		};
+
 		cpufreq_hw: cpufreq@fd91000 {
 			compatible = "qcom,shikra-epss";
 			reg = <0x0 0x0fd91000 0x0 0x1000>,

-- 
2.34.1