[PATCH v2 3/3] PCI: dwc: Expose endpoint DMA resources

[Koichiro Den]

Expose the DesignWare endpoint-integrated eDMA register window and
linked-list descriptor memories through the EPC auxiliary resource API.
This lets endpoint functions decide which channels to publish to the host.

When the DMA register window is already visible through a reserved BAR
region, report its BAR and offset. Otherwise report it as a normal
physical resource so an endpoint function can map it. Descriptor resources
also carry dmaengine filter information so consumers can claim exact
channels before delegation.

Signed-off-by: Koichiro Den <den@xxxxxxxxxxxxx>
---
Changes in v2:
  - Follow the part 1/3 v2 channel-claim model by publishing DMAengine
    filter information instead of calling dw_edma_find_channel().

 .../pci/controller/dwc/pcie-designware-ep.c   | 91 ++++++++++++++++++-
 1 file changed, 87 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index e4c6f7193495..90a44be0287d 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -866,14 +866,38 @@ dw_pcie_ep_get_aux_resources_count(struct pci_epc *epc, u8 func_no,
 	struct dw_pcie_ep *ep = epc_get_drvdata(epc);
 	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 	struct dw_edma_chip *edma = &pci->edma;
+	unsigned int i;
+	int count = 1;
 
 	if (!pci->edma_reg_size)
 		return 0;
 
-	if (edma->db_offset == ~0)
-		return 0;
+	for (i = 0; i < edma->ll_wr_cnt; i++) {
+		if (edma->ll_region_wr[i].sz)
+			count++;
+	}
+
+	for (i = 0; i < edma->ll_rd_cnt; i++) {
+		if (edma->ll_region_rd[i].sz)
+			count++;
+	}
+
+	if (edma->db_offset != ~0)
+		count++;
+
+	return count;
+}
+
+static bool dw_pcie_ep_dma_filter_fn(struct dma_chan *chan, void *param)
+{
+	const struct pci_epc_aux_resource *res = param;
+	struct dw_edma_hw_chan_filter filter = {
+		.dma_dev = res->u.dma_desc.dma_dev,
+		.write = res->u.dma_desc.dir == PCI_EPC_AUX_DMA_EP_TO_RC,
+		.id = res->u.dma_desc.hw_ch,
+	};
 
-	return 1;
+	return dw_edma_filter_hw_chan(chan, &filter);
 }
 
 static int
@@ -889,6 +913,7 @@ dw_pcie_ep_get_aux_resources(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
 	resource_size_t db_offset = edma->db_offset;
 	resource_size_t dma_ctrl_bar_offset = 0;
 	resource_size_t dma_reg_size;
+	unsigned int i;
 	int count;
 
 	count = dw_pcie_ep_get_aux_resources_count(epc, func_no, vfunc_no);
@@ -910,6 +935,64 @@ dw_pcie_ep_get_aux_resources(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
 	if (rsvd && rsvd->size < dma_reg_size)
 		dma_reg_size = rsvd->size;
 
+	count = 0;
+	resources[count++] = (struct pci_epc_aux_resource) {
+		.type = PCI_EPC_AUX_DMA_CTRL_MMIO,
+		.phys_addr = pci->edma_reg_phys,
+		.size = dma_reg_size,
+		.bar = dma_ctrl_bar,
+		.bar_offset = dma_ctrl_bar != NO_BAR ? dma_ctrl_bar_offset : 0,
+		.u.dma_ctrl = {
+			.reg_layout = PCI_EPC_AUX_DMA_REG_LAYOUT_DW_EDMA,
+			.reg_layout_data = edma->mf,
+			.ep_to_rc_ch_cnt = edma->ll_wr_cnt,
+			.rc_to_ep_ch_cnt = edma->ll_rd_cnt,
+		},
+	};
+
+	for (i = 0; i < edma->ll_wr_cnt; i++) {
+		struct dw_edma_region *ll = &edma->ll_region_wr[i];
+
+		if (!ll->sz)
+			continue;
+
+		resources[count++] = (struct pci_epc_aux_resource) {
+			.type = PCI_EPC_AUX_DMA_DESC_MEM,
+			.phys_addr = ll->paddr,
+			.size = ll->sz,
+			.bar = NO_BAR,
+			.u.dma_desc = {
+				.dir = PCI_EPC_AUX_DMA_EP_TO_RC,
+				.hw_ch = i,
+				.dma_dev = edma->dev,
+				.filter_fn = dw_pcie_ep_dma_filter_fn,
+			},
+		};
+	}
+
+	for (i = 0; i < edma->ll_rd_cnt; i++) {
+		struct dw_edma_region *ll = &edma->ll_region_rd[i];
+
+		if (!ll->sz)
+			continue;
+
+		resources[count++] = (struct pci_epc_aux_resource) {
+			.type = PCI_EPC_AUX_DMA_DESC_MEM,
+			.phys_addr = ll->paddr,
+			.size = ll->sz,
+			.bar = NO_BAR,
+			.u.dma_desc = {
+				.dir = PCI_EPC_AUX_DMA_RC_TO_EP,
+				.hw_ch = i,
+				.dma_dev = edma->dev,
+				.filter_fn = dw_pcie_ep_dma_filter_fn,
+			},
+		};
+	}
+
+	if (db_offset == ~0)
+		return 0;
+
 	/*
 	 * For interrupt-emulation doorbells, report a standalone resource
 	 * instead of bundling it into the DMA controller MMIO resource.
@@ -918,7 +1001,7 @@ dw_pcie_ep_get_aux_resources(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
 				  sizeof(u32), dma_reg_size))
 		return -EINVAL;
 
-	resources[0] = (struct pci_epc_aux_resource) {
+	resources[count] = (struct pci_epc_aux_resource) {
 		.type = PCI_EPC_AUX_DOORBELL_MMIO,
 		.phys_addr = pci->edma_reg_phys + db_offset,
 		.size = sizeof(u32),
-- 
2.51.0