[PATCH v7 16/18] ASoC: rsnd: src: Add SRC reset support for RZ/G3E
From: John Madieu
Date: Mon May 25 2026 - 07:07:52 EST
The RZ/G3E SoC exposes a shared SCU reset controller used by all SRC
modules. Acquire it once and pass it through per-instance's
rsnd_mod_init() so it is wired into the rsnd_mod->rstc plumbing.
devm_reset_control_get_optional_shared() returns NULL when no reset
is described in DT, leaving existing R-Car generations unaffected.
Signed-off-by: John Madieu <john.madieu.xa@xxxxxxxxxxxxxx>
---
Changes:
v7: New patch. Split out of [PATCH v6 14/16] "ASoC: rsnd: src: Add
SRC reset and clock support for RZ/G3E" per Kuninori Morimoto's
request. This patch carries only the shared "scu" reset
acquisition and its rsnd_mod_init() plumbing.
- Acquire the shared "scu" reset once, before the per-SRC probe
loop, instead of inside it.
sound/soc/renesas/rcar/src.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/sound/soc/renesas/rcar/src.c b/sound/soc/renesas/rcar/src.c
index 88ea9aad5cae..cad15fcc37f2 100644
--- a/sound/soc/renesas/rcar/src.c
+++ b/sound/soc/renesas/rcar/src.c
@@ -720,6 +720,7 @@ int rsnd_src_probe(struct rsnd_priv *priv)
{
struct device_node *node;
struct device *dev = rsnd_priv_to_dev(priv);
+ struct reset_control *rstc;
struct rsnd_src_ctrl *src_ctrl;
struct rsnd_src *src;
struct clk *clk;
@@ -772,6 +773,16 @@ int rsnd_src_probe(struct rsnd_priv *priv)
goto rsnd_src_probe_done;
}
+ /*
+ * Shared SCU reset for every SRC module; acquire once.
+ * R-Car platforms typically don't have SRC reset controls.
+ */
+ rstc = devm_reset_control_get_optional_shared(dev, "scu");
+ if (IS_ERR(rstc)) {
+ ret = PTR_ERR(rstc);
+ goto rsnd_src_probe_done;
+ }
+
i = 0;
for_each_child_of_node_scoped(node, np) {
if (!of_device_is_available(np))
@@ -798,7 +809,7 @@ int rsnd_src_probe(struct rsnd_priv *priv)
}
ret = rsnd_mod_init(priv, rsnd_mod_get(src),
- &rsnd_src_ops, clk, NULL, RSND_MOD_SRC, i);
+ &rsnd_src_ops, clk, rstc, RSND_MOD_SRC, i);
if (ret)
goto rsnd_src_probe_done;
--
2.25.1