[PATCH v4 2/8] clk: renesas: r9a09g047: Add audio clock and reset support
From: John Madieu
Date: Mon May 25 2026 - 07:10:14 EST
Add clock and reset entries for audio-related modules on the RZ/G3E SoC.
Target modules are:
- SSIU (Serial Sound Interface Unit) with SSI ch0-ch9
- SCU (Sampling Rate Converter Unit) with SRC ch0-ch9, DVC ch0-ch1,
CTU/MIX ch0-ch1
- DMACpp (Audio DMA Controller)
- ADG (Audio Clock Generator) with divider input clocks and audio
master clock outputs
The ADG SSI clock outputs (adg_ssi[0-9]_clk) are parented on
CLK_PLLCLN_DIV8 as a deliberate simplification: the ADG dynamically
muxes each output between adg_0_clk_195m and audio_clk[a,b,c] at
runtime via ADG_AUDIO_CLK_SEL{0,1,2}, owned by the rsnd-adg driver.
While at it, reorder plldty_div16 to group it with the other plldty
fixed dividers.
Signed-off-by: John Madieu <john.madieu.xa@xxxxxxxxxxxxxx>
---
Changes:
v4:
- Drop CLK_AUDIO_CLKA and its DEF_INPUT("audio_clka") entry, and
reparent adg_0_audio_clka on CLK_AUDIO_EXTAL, since AUDIO_CLKA is
provided by the existing AUDIO_EXTAL pin (Geert Uytterhoeven).
- Drop the internal core clocks Geert flagged as unused:
pllcm33_div4_ddiv2, pllcm33_div4_ddiv2_div2, pllcln_div32,
plldty_div2, plldty_div4 and cdiv5_mainosc. pllcln_div4 is kept,
as scu_0_clkx2 is parented on it.
- Rename the audio module clocks as suggested by Geert: ssif_clk ->
ssif_0_clk, scu_clk -> scu_0_clk, scu_clkx2 -> scu_0_clkx2,
admac_clk -> dmacpp_0_clk, adg_clks1 -> adg_0_clks1, adg_clk_200m
-> adg_0_clk_195m, adg_audio_clk{a,b,c} -> adg_0_audio_clk{a,b,c},
ssif_supply_clk -> ssiu_supply_clk. Update the target-module list
in the commit message (ADMAC -> DMACpp) to match.
- Rename the audio reset entries as suggested by Geert: SCU_RESET_SRU
-> SCU_0_RESET_SRU, ADMAC_ARESETN -> DMACpp_0_ARST,
ADG_RST_RESET_ADG -> ADG_0_RST_RESET_ADG.
- The adg_ssi[0-9]_clk parent is left unchanged as CLK_PLLCLN_DIV8.
Geert questioned whether this is correct, since these clocks are
ADG-generated. The parent is not changed; instead the commit
message now documents that the ADG muxes each output between
adg_0_clk_195m and audio_clk[a,b,c] at runtime via
ADG_AUDIO_CLK_SEL{0,1,2}, which no static parent can describe.
v3: No changes
v2: No changes
drivers/clk/renesas/r9a09g047-cpg.c | 112 +++++++++++++++++++++++++++-
1 file changed, 111 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index 94158b6834e6..c410a5d6a955 100644
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -23,6 +23,8 @@ enum clk_ids {
CLK_AUDIO_EXTAL,
CLK_RTXIN,
CLK_QEXTAL,
+ CLK_AUDIO_CLKB,
+ CLK_AUDIO_CLKC,
/* PLL Clocks */
CLK_PLLCM33,
@@ -44,6 +46,7 @@ enum clk_ids {
CLK_SMUX2_XSPI_CLK1,
CLK_PLLCM33_XSPI,
CLK_PLLCLN_DIV2,
+ CLK_PLLCLN_DIV4,
CLK_PLLCLN_DIV8,
CLK_PLLCLN_DIV16,
CLK_PLLCLN_DIV20,
@@ -159,6 +162,8 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
DEF_INPUT("rtxin", CLK_RTXIN),
DEF_INPUT("qextal", CLK_QEXTAL),
+ DEF_INPUT("audio_clkb", CLK_AUDIO_CLKB),
+ DEF_INPUT("audio_clkc", CLK_AUDIO_CLKC),
/* PLL Clocks */
DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
@@ -183,6 +188,7 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
DEF_CSDIV(".pllcm33_xspi", CLK_PLLCM33_XSPI, CLK_SMUX2_XSPI_CLK1, CSDIV0_DIVCTL3,
dtable_2_16),
DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
+ DEF_FIXED(".pllcln_div4", CLK_PLLCLN_DIV4, CLK_PLLCLN, 1, 4),
DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
DEF_FIXED(".pllcln_div20", CLK_PLLCLN_DIV20, CLK_PLLCLN, 1, 20),
@@ -194,6 +200,7 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
+ DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
@@ -205,7 +212,6 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
- DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
DEF_DDIV(".plldty_rcpu", CLK_PLLDTY_RCPU, CLK_PLLDTY, CDDIV3_DIVCTL2, dtable_2_64),
DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4),
@@ -532,6 +538,96 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
BUS_MSTOP(3, BIT(4))),
DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10,
BUS_MSTOP(2, BIT(15))),
+ DEF_MOD("ssif_0_clk", CLK_PLLCLN_DIV8, 15, 5, 7, 21,
+ BUS_MSTOP(2, BIT(3) | BIT(4))),
+ DEF_MOD("scu_0_clk", CLK_PLLCLN_DIV8, 15, 6, 7, 22,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("scu_0_clkx2", CLK_PLLCLN_DIV4, 15, 7, 7, 23,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("dmacpp_0_clk", CLK_PLLCLN_DIV8, 15, 8, 7, 24,
+ BUS_MSTOP(2, BIT(5))),
+ DEF_MOD("adg_0_clks1", CLK_PLLCLN_DIV8, 15, 9, 7, 25,
+ BUS_MSTOP(2, BIT(2))),
+ DEF_MOD("adg_0_clk_195m", CLK_PLLCLN_DIV8, 15, 10, 7, 26,
+ BUS_MSTOP(2, BIT(2))),
+ DEF_MOD("adg_0_audio_clka", CLK_AUDIO_EXTAL, 15, 11, 7, 27,
+ BUS_MSTOP(2, BIT(2))),
+ DEF_MOD("adg_0_audio_clkb", CLK_AUDIO_CLKB, 15, 12, 7, 28,
+ BUS_MSTOP(2, BIT(2))),
+ DEF_MOD("adg_0_audio_clkc", CLK_AUDIO_CLKC, 15, 13, 7, 29,
+ BUS_MSTOP(2, BIT(2))),
+ DEF_MOD("adg_ssi0_clk", CLK_PLLCLN_DIV8, 22, 0, -1, -1,
+ BUS_MSTOP(2, BIT(2))),
+ DEF_MOD("adg_ssi1_clk", CLK_PLLCLN_DIV8, 22, 1, -1, -1,
+ BUS_MSTOP(2, BIT(2))),
+ DEF_MOD("adg_ssi2_clk", CLK_PLLCLN_DIV8, 22, 2, -1, -1,
+ BUS_MSTOP(2, BIT(2))),
+ DEF_MOD("adg_ssi3_clk", CLK_PLLCLN_DIV8, 22, 3, -1, -1,
+ BUS_MSTOP(2, BIT(2))),
+ DEF_MOD("adg_ssi4_clk", CLK_PLLCLN_DIV8, 22, 4, -1, -1,
+ BUS_MSTOP(2, BIT(2))),
+ DEF_MOD("adg_ssi5_clk", CLK_PLLCLN_DIV8, 22, 5, -1, -1,
+ BUS_MSTOP(2, BIT(2))),
+ DEF_MOD("adg_ssi6_clk", CLK_PLLCLN_DIV8, 22, 6, -1, -1,
+ BUS_MSTOP(2, BIT(2))),
+ DEF_MOD("adg_ssi7_clk", CLK_PLLCLN_DIV8, 22, 7, -1, -1,
+ BUS_MSTOP(2, BIT(2))),
+ DEF_MOD("adg_ssi8_clk", CLK_PLLCLN_DIV8, 22, 8, -1, -1,
+ BUS_MSTOP(2, BIT(2))),
+ DEF_MOD("adg_ssi9_clk", CLK_PLLCLN_DIV8, 22, 9, -1, -1,
+ BUS_MSTOP(2, BIT(2))),
+ DEF_MOD("dvc0_clk", CLK_PLLCLN_DIV8, 23, 0, -1, -1,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("dvc1_clk", CLK_PLLCLN_DIV8, 23, 1, -1, -1,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("ctu0_mix0_clk", CLK_PLLCLN_DIV8, 23, 2, -1, -1,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("ctu1_mix1_clk", CLK_PLLCLN_DIV8, 23, 3, -1, -1,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("src0_clk", CLK_PLLCLN_DIV8, 23, 4, -1, -1,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("src1_clk", CLK_PLLCLN_DIV8, 23, 5, -1, -1,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("src2_clk", CLK_PLLCLN_DIV8, 23, 6, -1, -1,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("src3_clk", CLK_PLLCLN_DIV8, 23, 7, -1, -1,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("src4_clk", CLK_PLLCLN_DIV8, 23, 8, -1, -1,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("src5_clk", CLK_PLLCLN_DIV8, 23, 9, -1, -1,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("src6_clk", CLK_PLLCLN_DIV8, 23, 10, -1, -1,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("src7_clk", CLK_PLLCLN_DIV8, 23, 11, -1, -1,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("src8_clk", CLK_PLLCLN_DIV8, 23, 12, -1, -1,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("src9_clk", CLK_PLLCLN_DIV8, 23, 13, -1, -1,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("scu_supply_clk", CLK_PLLCLN_DIV8, 23, 14, -1, -1,
+ BUS_MSTOP(2, BIT(0) | BIT(1))),
+ DEF_MOD("ssiu_supply_clk", CLK_PLLCLN_DIV8, 24, 0, -1, -1,
+ BUS_MSTOP(2, BIT(3) | BIT(4))),
+ DEF_MOD("ssi0_clk", CLK_PLLCLN_DIV8, 24, 1, -1, -1,
+ BUS_MSTOP(2, BIT(3) | BIT(4))),
+ DEF_MOD("ssi1_clk", CLK_PLLCLN_DIV8, 24, 2, -1, -1,
+ BUS_MSTOP(2, BIT(3) | BIT(4))),
+ DEF_MOD("ssi2_clk", CLK_PLLCLN_DIV8, 24, 3, -1, -1,
+ BUS_MSTOP(2, BIT(3) | BIT(4))),
+ DEF_MOD("ssi3_clk", CLK_PLLCLN_DIV8, 24, 4, -1, -1,
+ BUS_MSTOP(2, BIT(3) | BIT(4))),
+ DEF_MOD("ssi4_clk", CLK_PLLCLN_DIV8, 24, 5, -1, -1,
+ BUS_MSTOP(2, BIT(3) | BIT(4))),
+ DEF_MOD("ssi5_clk", CLK_PLLCLN_DIV8, 24, 6, -1, -1,
+ BUS_MSTOP(2, BIT(3) | BIT(4))),
+ DEF_MOD("ssi6_clk", CLK_PLLCLN_DIV8, 24, 7, -1, -1,
+ BUS_MSTOP(2, BIT(3) | BIT(4))),
+ DEF_MOD("ssi7_clk", CLK_PLLCLN_DIV8, 24, 8, -1, -1,
+ BUS_MSTOP(2, BIT(3) | BIT(4))),
+ DEF_MOD("ssi8_clk", CLK_PLLCLN_DIV8, 24, 9, -1, -1,
+ BUS_MSTOP(2, BIT(3) | BIT(4))),
+ DEF_MOD("ssi9_clk", CLK_PLLCLN_DIV8, 24, 10, -1, -1,
+ BUS_MSTOP(2, BIT(3) | BIT(4))),
DEF_MOD("dsi_0_vclk2", CLK_SMUX2_DSI1_CLK, 25, 0, 10, 21,
BUS_MSTOP(9, BIT(15) | BIT(14))),
DEF_MOD("lcdc_1_clk_a", CLK_PLLDTY_ACPU_DIV2, 26, 8, 10, 30,
@@ -621,6 +717,20 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
DEF_RST(13, 13, 6, 14), /* GE3D_RESETN */
DEF_RST(13, 14, 6, 15), /* GE3D_AXI_RESETN */
DEF_RST(13, 15, 6, 16), /* GE3D_ACE_RESETN */
+ DEF_RST(14, 1, 6, 18), /* SSIF_0_ASYNC_RESET_SSI */
+ DEF_RST(14, 2, 6, 19), /* SSIF_0_SYNC_RESET_SSI0 */
+ DEF_RST(14, 3, 6, 20), /* SSIF_0_SYNC_RESET_SSI1 */
+ DEF_RST(14, 4, 6, 21), /* SSIF_0_SYNC_RESET_SSI2 */
+ DEF_RST(14, 5, 6, 22), /* SSIF_0_SYNC_RESET_SSI3 */
+ DEF_RST(14, 6, 6, 23), /* SSIF_0_SYNC_RESET_SSI4 */
+ DEF_RST(14, 7, 6, 24), /* SSIF_0_SYNC_RESET_SSI5 */
+ DEF_RST(14, 8, 6, 25), /* SSIF_0_SYNC_RESET_SSI6 */
+ DEF_RST(14, 9, 6, 26), /* SSIF_0_SYNC_RESET_SSI7 */
+ DEF_RST(14, 10, 6, 27), /* SSIF_0_SYNC_RESET_SSI8 */
+ DEF_RST(14, 11, 6, 28), /* SSIF_0_SYNC_RESET_SSI9 */
+ DEF_RST(14, 12, 6, 29), /* SCU_0_RESET_SRU */
+ DEF_RST(14, 13, 6, 30), /* DMACpp_0_ARST */
+ DEF_RST(14, 14, 6, 31), /* ADG_0_RST_RESET_ADG */
DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */
DEF_RST(17, 14, 8, 15), /* LCDC_1_RESET_N */
};
--
2.25.1