Re: [PATCH] mips: cps: Assemble jr.hb with an R2 ISA level

[Thomas Bogendoerfer]

On Thu, May 07, 2026 at 04:23:23PM -0700, Rosen Penev wrote:
> A MIPS allmodconfig built with LLVM can select CPU_MIPS32_R1 together
> with MIPS_MT_SMP. In that configuration clang invokes the integrated
> assembler with -march=mips32, and the MIPS MT path in cps-vec.S fails
> to assemble two jr.hb instructions:
> 
>   arch/mips/kernel/cps-vec.S:376:2: error: instruction requires
>   a CPU feature not currently enabled
> 
>   arch/mips/kernel/cps-vec.S:490:4: error: instruction requires
>   a CPU feature not currently enabled
> 
> The earlier jr.hb in the same file is already assembled inside a .set
> MIPS_ISA_LEVEL_RAW scope. The two failing sites are reached after
> popping back to the file's base ISA level, so LLVM correctly rejects
> them for an R1 target.
> 
> Wrap those jr.hb instructions in the same ISA-level push/pop used by
> the working site. This keeps the MT code unchanged while making the
> required R2 hazard-branch encoding explicit to the assembler.
> 
> Assisted-by: Codex:GPT-5.5
> Signed-off-by: Rosen Penev <rosenp@xxxxxxxxx>
> ---
>  arch/mips/kernel/cps-vec.S | 6 ++++++
>  1 file changed, 6 insertions(+)

applied to mips-next

Thomas.

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