RE: [EXTERNAL] Re: [PATCH v6 1/2] dt-bindings: perf: marvell: Extend CN10K DDR PMU binding for CN20K

[Geethasowjanya Akula]

>-----Original Message-----
>From: Krzysztof Kozlowski <krzk@xxxxxxxxxx>
>Sent: Wednesday, May 27, 2026 2:15 PM
>To: Geethasowjanya Akula <gakula@xxxxxxxxxxx>
>Cc: linux-perf-users@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; linux-arm-
>kernel@xxxxxxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx;
>mark.rutland@xxxxxxx; will@xxxxxxxxxx; krzk+dt@xxxxxxxxxx
>Subject: [EXTERNAL] Re: [PATCH v6 1/2] dt-bindings: perf: marvell: Extend
>CN10K DDR PMU binding for CN20K
>
>On Tue, May 26, 2026 at 10:13:29PM +0530, Geetha sowjanya wrote:
>> Marvell CN20K SoCs integrate a DDR Performance Monitoring Unit (PMU)
>> associated with the DDR controller. The block provides hardware
>> counters to monitor DDR traffic and performance events and is accessed
>> via a dedicated MMIO region.
>>
>> The CN20K DDR PMU is functionally equivalent to the CN10K DDR PMU,
>> with minor register offset differences.
>>
>> Changes in v6:
>> - dt-bindings: Document CN20K in the existing marvell-cn10k-ddr.yaml;
>>   add maintainer, description, compatible enum entry, and a CN20K example
>>   with unit-address aligned to reg.
>
>Changelog is not part of commit msg, but changelog area, so after ---.
Will fix it in next version.
>
>>
>> Signed-off-by: Geetha sowjanya <gakula@xxxxxxxxxxx>
>> ---
>>  .../bindings/perf/marvell-cn10k-ddr.yaml       | 18 +++++++++++++++++-
>>  1 file changed, 17 insertions(+), 1 deletion(-)
>>
>> diff --git
>> a/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml
>> b/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml
>> index a18dd0a8c43a..79fae9fdb6f1 100644
>> --- a/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml
>> +++ b/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml
>> @@ -4,16 +4,22 @@
>>  $id:
>> https://urldefense.proofpoint.com/v2/url?u=http-3A__devicetree.org_sch
>> emas_perf_marvell-2Dcn10k-2Dddr.yaml-
>23&d=DwIBaQ&c=nKjWec2b6R0mOyPaz7x
>>
>tfQ&r=UiEt_nUeYFctu7JVLXVlXDhTmq_EAfooaZEYInfGuEQ&m=KPupvCgvILuS9
>YRzKR
>>
>VMAwO0JiUqPQ1YTbqas_YAp_UUtzzdUgNdMbBRq73VWzCK&s=QEQyFv8YKF
>DGoUxGi46U7
>> YjmvjHKHqDmzoGi2ww3GLQ&e=
>>  $schema:
>> https://urldefense.proofpoint.com/v2/url?u=http-3A__devicetree.org_met
>> a-2Dschemas_core.yaml-
>23&d=DwIBaQ&c=nKjWec2b6R0mOyPaz7xtfQ&r=UiEt_nUeY
>>
>Fctu7JVLXVlXDhTmq_EAfooaZEYInfGuEQ&m=KPupvCgvILuS9YRzKRVMAwO0Ji
>UqPQ1YT
>>
>bqas_YAp_UUtzzdUgNdMbBRq73VWzCK&s=3kP4V_gIcxiXPm4vOCnsrP8hkM0y
>HL6lTEfo
>> 9X3fVno&e=
>>
>> -title: Marvell CN10K DDR performance monitor
>> +title: Marvell CN10K / CN20K DDR performance monitor
>> +
>> +description:
>> +  Performance Monitoring Unit (PMU) for the DDR controller on Marvell
>> +  CN10K and CN20K SoCs. The block is accessed via a dedicated MMIO
>region.
>>
>>  maintainers:
>>    - Bharat Bhushan <bbhushan2@xxxxxxxxxxx>
>> +  - Geetha sowjanya <gakula@xxxxxxxxxxx>
>>
>>  properties:
>>    compatible:
>>      items:
>>        - enum:
>>            - marvell,cn10k-ddr-pmu
>> +          - marvell,cn20k-ddr-pmu
>>
>>    reg:
>>      maxItems: 1
>> @@ -35,3 +41,13 @@ examples:
>>              reg = <0x87e1 0xc0000000 0x0 0x10000>;
>>          };
>>      };
>> +  - |
>> +    bus {
>> +        #address-cells = <2>;
>> +        #size-cells = <2>;
>> +
>> +        pmu@c20000000000 {
>> +            compatible = "marvell,cn20k-ddr-pmu";
>> +            reg = <0xc200 0x00000000 0x0 0x100000>;
>
>No need for a new example.
Added the example because the register address range differs from CN10K, and a separate example makes the CN20K mapping explicit.
As suggested will drop the additional example in next version.

Thanks,
Geetha.
>
>Best regards,
>Krzysztof