[PATCH net-next v4 2/4] dpll: zl3073x: use per-operation poll timeouts
From: Ivan Vecera
Date: Wed May 27 2026 - 12:20:00 EST
Replace the single 2s timeout in zl3073x_poll_zero_u8() with a
per-caller timeout parameter. Different HW operations have different
expected completion times so using per-operation timeouts improves
error detection. The timeout values are based on proprietary source
code provided by Microchip and own measurement.
Signed-off-by: Ivan Vecera <ivecera@xxxxxxxxxx>
---
drivers/dpll/zl3073x/chan.c | 6 ++++--
drivers/dpll/zl3073x/core.c | 29 +++++++++++++++++------------
drivers/dpll/zl3073x/core.h | 10 +++++++++-
3 files changed, 30 insertions(+), 15 deletions(-)
diff --git a/drivers/dpll/zl3073x/chan.c b/drivers/dpll/zl3073x/chan.c
index 2fe3c3da84bb5..677a920c16254 100644
--- a/drivers/dpll/zl3073x/chan.c
+++ b/drivers/dpll/zl3073x/chan.c
@@ -33,7 +33,8 @@ int zl3073x_chan_state_update(struct zl3073x_dev *zldev, u8 index)
/* Read df_offset vs tracked reference */
rc = zl3073x_poll_zero_u8(zldev, ZL_REG_DPLL_DF_READ(index),
- ZL_DPLL_DF_READ_SEM);
+ ZL_DPLL_DF_READ_SEM,
+ ZL_POLL_DF_READ_TIMEOUT_US);
if (rc)
return rc;
@@ -43,7 +44,8 @@ int zl3073x_chan_state_update(struct zl3073x_dev *zldev, u8 index)
return rc;
rc = zl3073x_poll_zero_u8(zldev, ZL_REG_DPLL_DF_READ(index),
- ZL_DPLL_DF_READ_SEM);
+ ZL_DPLL_DF_READ_SEM,
+ ZL_POLL_DF_READ_TIMEOUT_US);
if (rc)
return rc;
diff --git a/drivers/dpll/zl3073x/core.c b/drivers/dpll/zl3073x/core.c
index b3345060490db..02f42fd72aa57 100644
--- a/drivers/dpll/zl3073x/core.c
+++ b/drivers/dpll/zl3073x/core.c
@@ -311,17 +311,17 @@ int zl3073x_write_u48(struct zl3073x_dev *zldev, unsigned int reg, u64 val)
* @zldev: zl3073x device pointer
* @reg: register to poll (has to be 8bit register)
* @mask: bit mask for polling
+ * @timeout_us: timeout in microseconds
*
* Waits for bits specified by @mask in register @reg value to be cleared
* by the device.
*
* Returns: 0 on success, <0 on error
*/
-int zl3073x_poll_zero_u8(struct zl3073x_dev *zldev, unsigned int reg, u8 mask)
+int zl3073x_poll_zero_u8(struct zl3073x_dev *zldev, unsigned int reg,
+ u8 mask, unsigned int timeout_us)
{
- /* Register polling sleep & timeout */
-#define ZL_POLL_SLEEP_US 10
-#define ZL_POLL_TIMEOUT_US 2000000
+#define ZL_POLL_SLEEP_US 10
unsigned int val;
/* Check the register is 8bit */
@@ -335,7 +335,7 @@ int zl3073x_poll_zero_u8(struct zl3073x_dev *zldev, unsigned int reg, u8 mask)
reg = ZL_REG_ADDR(reg) + ZL_RANGE_OFFSET;
return regmap_read_poll_timeout(zldev->regmap, reg, val, !(val & mask),
- ZL_POLL_SLEEP_US, ZL_POLL_TIMEOUT_US);
+ ZL_POLL_SLEEP_US, timeout_us);
}
int zl3073x_mb_op(struct zl3073x_dev *zldev, unsigned int op_reg, u8 op_val,
@@ -354,7 +354,8 @@ int zl3073x_mb_op(struct zl3073x_dev *zldev, unsigned int op_reg, u8 op_val,
return rc;
/* Wait for the operation to actually finish */
- return zl3073x_poll_zero_u8(zldev, op_reg, op_val);
+ return zl3073x_poll_zero_u8(zldev, op_reg, op_val,
+ ZL_POLL_MB_TIMEOUT_US);
}
/**
@@ -377,8 +378,8 @@ zl3073x_do_hwreg_op(struct zl3073x_dev *zldev, u8 op)
return rc;
/* Poll for completion - pending bit cleared */
- return zl3073x_poll_zero_u8(zldev, ZL_REG_HWREG_OP,
- ZL_HWREG_OP_PENDING);
+ return zl3073x_poll_zero_u8(zldev, ZL_REG_HWREG_OP, ZL_HWREG_OP_PENDING,
+ ZL_POLL_HWREG_TIMEOUT_US);
}
/**
@@ -609,7 +610,8 @@ int zl3073x_ref_phase_offsets_update(struct zl3073x_dev *zldev, int channel)
* to be zero to ensure that the measured data are coherent.
*/
rc = zl3073x_poll_zero_u8(zldev, ZL_REG_REF_PHASE_ERR_READ_RQST,
- ZL_REF_PHASE_ERR_READ_RQST_RD);
+ ZL_REF_PHASE_ERR_READ_RQST_RD,
+ ZL_POLL_PHASE_ERR_TIMEOUT_US);
if (rc)
return rc;
@@ -628,7 +630,8 @@ int zl3073x_ref_phase_offsets_update(struct zl3073x_dev *zldev, int channel)
/* Wait for finish */
return zl3073x_poll_zero_u8(zldev, ZL_REG_REF_PHASE_ERR_READ_RQST,
- ZL_REF_PHASE_ERR_READ_RQST_RD);
+ ZL_REF_PHASE_ERR_READ_RQST_RD,
+ ZL_POLL_PHASE_ERR_TIMEOUT_US);
}
/**
@@ -648,7 +651,8 @@ zl3073x_ref_freq_meas_latch(struct zl3073x_dev *zldev, u8 type)
/* Wait for previous measurement to finish */
rc = zl3073x_poll_zero_u8(zldev, ZL_REG_REF_FREQ_MEAS_CTRL,
- ZL_REF_FREQ_MEAS_CTRL);
+ ZL_REF_FREQ_MEAS_CTRL,
+ ZL_POLL_FREQ_MEAS_TIMEOUT_US);
if (rc)
return rc;
@@ -669,7 +673,8 @@ zl3073x_ref_freq_meas_latch(struct zl3073x_dev *zldev, u8 type)
/* Wait for finish */
return zl3073x_poll_zero_u8(zldev, ZL_REG_REF_FREQ_MEAS_CTRL,
- ZL_REF_FREQ_MEAS_CTRL);
+ ZL_REF_FREQ_MEAS_CTRL,
+ ZL_POLL_FREQ_MEAS_TIMEOUT_US);
}
/**
diff --git a/drivers/dpll/zl3073x/core.h b/drivers/dpll/zl3073x/core.h
index 99440620407da..d470845ee12ae 100644
--- a/drivers/dpll/zl3073x/core.h
+++ b/drivers/dpll/zl3073x/core.h
@@ -7,6 +7,7 @@
#include <linux/kthread.h>
#include <linux/list.h>
#include <linux/mutex.h>
+#include <linux/time64.h>
#include <linux/types.h>
#include "chan.h"
@@ -19,6 +20,12 @@ struct device;
struct regmap;
struct zl3073x_dpll;
+/* Per-operation poll timeouts */
+#define ZL_POLL_DF_READ_TIMEOUT_US (25 * USEC_PER_MSEC)
+#define ZL_POLL_FREQ_MEAS_TIMEOUT_US (50 * USEC_PER_MSEC)
+#define ZL_POLL_HWREG_TIMEOUT_US (50 * USEC_PER_MSEC)
+#define ZL_POLL_MB_TIMEOUT_US (30 * USEC_PER_MSEC)
+#define ZL_POLL_PHASE_ERR_TIMEOUT_US (50 * USEC_PER_MSEC)
enum zl3073x_flags {
ZL3073X_FLAG_REF_PHASE_COMP_32_BIT,
@@ -125,7 +132,8 @@ struct zl3073x_hwreg_seq_item {
int zl3073x_mb_op(struct zl3073x_dev *zldev, unsigned int op_reg, u8 op_val,
unsigned int mask_reg, u16 mask_val);
-int zl3073x_poll_zero_u8(struct zl3073x_dev *zldev, unsigned int reg, u8 mask);
+int zl3073x_poll_zero_u8(struct zl3073x_dev *zldev, unsigned int reg,
+ u8 mask, unsigned int timeout_us);
int zl3073x_read_u8(struct zl3073x_dev *zldev, unsigned int reg, u8 *val);
int zl3073x_read_u16(struct zl3073x_dev *zldev, unsigned int reg, u16 *val);
int zl3073x_read_u32(struct zl3073x_dev *zldev, unsigned int reg, u32 *val);
--
2.53.0