RE: [PATCH 4/5] arm64: dts: renesas: rzg3l-smarc-som: Enable versa clock generator

[Biju Das]

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>
> Sent: 27 May 2026 17:14
> Subject: Re: [PATCH 4/5] arm64: dts: renesas: rzg3l-smarc-som: Enable versa clock generator
> 
> Hi Biju,
> 
> Thanks for your patch!
> 
> On Tue, 5 May 2026 at 14:37, Biju <biju.das.au@xxxxxxxxx> wrote:
> > From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> >
> > The RZ/G3L SMARC SoM has versa 5P35023B clock generator to generate
> > the below clocks:
> >   se1: AUDIO_MCK (11.2896 or 12.2880 MHz)
> >   se2: RZ_AUDIO_CLK_B (11.2896 MHz)
> >   se3: RZ_AUDIO_CLK_C (12.2880 MHz)
> >   diff{1,1B}: ET{0,1}_PHY_CLK (25 MHz)
> >   diff2{2,2B}: Not connected
> 
> All of these are listed in clock output index order...
> 
> >   ref: Not connected
> 
> ... except for "ref", which is the first output, so please move it to the top.

OK.

> 
> > Enable versa 5P35023B clock generator on the RZ/G3L SoM DTSI.
> >
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> 
> > --- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
> > @@ -40,6 +40,12 @@ memory@48000000 {
> >                 /* First 128MiB is reserved for secure area. */
> >                 reg = <0x0 0x48000000 0x0 0x78000000>;
> >         };
> > +
> > +       x2_clk: x2-clock {
> > +               compatible = "fixed-clock";
> > +               #clock-cells = <0>;
> > +               clock-frequency = <24000000>;
> > +       };
> >  };
> >
> >  &eth0 {
> > @@ -75,6 +81,20 @@ &extal_clk {
> >  &i2c0 {
> >         pinctrl-0 = <&i2c0_pins>;
> >         pinctrl-names = "default";
> > +
> > +       versa3: clock-generator@68 {
> > +               compatible = "renesas,5p35023";
> > +               reg = <0x68>;
> > +               #clock-cells = <1>;
> > +               clocks = <&x2_clk>;
> > +
> > +               assigned-clocks = <&versa3 0>, <&versa3 1>,
> > +                                 <&versa3 2>, <&versa3 3>,
> > +                                 <&versa3 4>, <&versa3 5>;
> > +               assigned-clock-rates = <24000000>, <12288000>,
> > +                                      <11289600>, <12288000>,
> > +                                      <25000000>, <25000000>;
> 
> Why do you set the clock rate of the (unused) ref output?

It is a mistake. will drop it.

> Copy-paste from the DT bindings example?

Yes, Will drop both the unused ref and diff2 output.

Cheers,
Biju
> 
> > +       };
> >  };
> >
> >  &mdio0 {
> \
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
> 
> In personal conversations with technical people, I call myself a hacker. But when I'm talking to
> journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds