Re: [PATCH v2] arm64: dts: renesas: rzt2h-n2h-evk: Configure eMMC/SDHI pins

From: Lad, Prabhakar

Date: Wed May 27 2026 - 14:13:04 EST

Hi Fabrizio,

Thank you for the patch.

On Thu, May 14, 2026 at 10:02 PM Fabrizio Castro
<fabrizio.castro.jz@xxxxxxxxxxx> wrote:
>
> The HW user manual for the Renesas RZ/T2H and the RZ/N2H states
> that for SDR104, SDR50, and HS200 to work properly the eMMC/SDHI
> interface pins have to be configured as specified below:
> * SDn_CLK pin - drive strength: Ultra High, slew rate: Fast
> * Other SDn_* pins: drive strength: High, slew rate: Fast,
> Schmitt trigger: disabled (not applicable to SDn_RST pins).
>
> HS DDR and DDR50 are currently not supported, and for every
> other bus mode the eMMC/SDHI interface pins should be configured
> as specified below:
> * SDn_CLK pin - drive strength: High, slew rate: Fast
> * Other SDn_* pins: drive strength: Middle, slew rate: Fast,
> Schmitt trigger: disabled (not applicable to SDn_RST pins).
>
> Adjust the pin definitions accordingly.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@xxxxxxxxxxx>
> ---
> v1->v2:
> * Take into account the settings for lower speed modes
>
> .../dts/renesas/rzt2h-n2h-evk-common.dtsi | 147 ++++++++++++++++--
> 1 file changed, 136 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
> index f87c2492f414..46f4aaac0478 100644
> --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
> @@ -275,12 +275,63 @@ data-pins {
> <RZT2H_PORT_PINMUX(12, 7, 0x29)>, /* SD0_DATA5 */
> <RZT2H_PORT_PINMUX(13, 0, 0x29)>, /* SD0_DATA6 */
> <RZT2H_PORT_PINMUX(13, 1, 0x29)>; /* SD0_DATA7 */
> + drive-strength-microamp = <5000>;
> + slew-rate = <1>;
> + input-schmitt-disable;
> };
>
> - ctrl-pins {
> - pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */
> - <RZT2H_PORT_PINMUX(12, 1, 0x29)>, /* SD0_CMD */
> - <RZT2H_PORT_PINMUX(13, 2, 0x29)>; /* SD0_RST# */
> + clk-pins {
> + pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>; /* SD0_CLK */
> + drive-strength-microamp = <9000>;
> + slew-rate = <1>;
> + };
> +
> + cmd-pins {
> + pinmux = <RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */
> + drive-strength-microamp = <5000>;
> + slew-rate = <1>;
> + input-schmitt-disable;
> + };
> +
> + rst-pins {
> + pinmux = <RZT2H_PORT_PINMUX(13, 2, 0x29)>; /* SD0_RST# */
> + drive-strength-microamp = <5000>;
> + slew-rate = <1>;
> + };
> + };
> +
> + sdhi0_emmc_pins_uhs: sd0-emmc-group-uhs {
This needs to be sd0-emmc-uhs-group and to keep it consistent, we can
rename sdhi0_emmc_pins_uhs to sdhi0_emmc_uhs_pins (and same for
below). Since Geert has already reviewed, perhaps this can be fixed up
while applying.

Rest LGTM,

Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>

Cheers,
Prabhakar

> + data-pins {
> + pinmux = <RZT2H_PORT_PINMUX(12, 2, 0x29)>, /* SD0_DATA0 */
> + <RZT2H_PORT_PINMUX(12, 3, 0x29)>, /* SD0_DATA1 */
> + <RZT2H_PORT_PINMUX(12, 4, 0x29)>, /* SD0_DATA2 */
> + <RZT2H_PORT_PINMUX(12, 5, 0x29)>, /* SD0_DATA3 */
> + <RZT2H_PORT_PINMUX(12, 6, 0x29)>, /* SD0_DATA4 */
> + <RZT2H_PORT_PINMUX(12, 7, 0x29)>, /* SD0_DATA5 */
> + <RZT2H_PORT_PINMUX(13, 0, 0x29)>, /* SD0_DATA6 */
> + <RZT2H_PORT_PINMUX(13, 1, 0x29)>; /* SD0_DATA7 */
> + drive-strength-microamp = <9000>;
> + slew-rate = <1>;
> + input-schmitt-disable;
> + };
> +
> + clk-pins {
> + pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>; /* SD0_CLK */
> + drive-strength-microamp = <11800>;
> + slew-rate = <1>;
> + };
> +
> + cmd-pins {
> + pinmux = <RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */
> + drive-strength-microamp = <9000>;
> + slew-rate = <1>;
> + input-schmitt-disable;
> + };
> +
> + rst-pins {
> + pinmux = <RZT2H_PORT_PINMUX(13, 2, 0x29)>; /* SD0_RST# */
> + drive-strength-microamp = <9000>;
> + slew-rate = <1>;
> };
> };
>
> @@ -299,12 +350,49 @@ data-pins {
> <RZT2H_PORT_PINMUX(12, 3, 0x29)>, /* SD0_DATA1 */
> <RZT2H_PORT_PINMUX(12, 4, 0x29)>, /* SD0_DATA2 */
> <RZT2H_PORT_PINMUX(12, 5, 0x29)>; /* SD0_DATA3 */
> + drive-strength-microamp = <5000>;
> + slew-rate = <1>;
> + input-schmitt-disable;
> + };
> +
> + clk-pins {
> + pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>; /* SD0_CLK */
> + drive-strength-microamp = <9000>;
> + slew-rate = <1>;
> };
>
> ctrl-pins {
> - pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */
> - <RZT2H_PORT_PINMUX(12, 1, 0x29)>, /* SD0_CMD */
> + pinmux = <RZT2H_PORT_PINMUX(12, 1, 0x29)>, /* SD0_CMD */
> <RZT2H_PORT_PINMUX(22, 5, 0x29)>; /* SD0_CD */
> + drive-strength-microamp = <5000>;
> + slew-rate = <1>;
> + input-schmitt-disable;
> + };
> + };
> +
> + sdhi0_sd_pins_uhs: sd0-sd-group-uhs {
> + data-pins {
> + pinmux = <RZT2H_PORT_PINMUX(12, 2, 0x29)>, /* SD0_DATA0 */
> + <RZT2H_PORT_PINMUX(12, 3, 0x29)>, /* SD0_DATA1 */
> + <RZT2H_PORT_PINMUX(12, 4, 0x29)>, /* SD0_DATA2 */
> + <RZT2H_PORT_PINMUX(12, 5, 0x29)>; /* SD0_DATA3 */
> + drive-strength-microamp = <9000>;
> + slew-rate = <1>;
> + input-schmitt-disable;
> + };
> +
> + clk-pins {
> + pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>; /* SD0_CLK */
> + drive-strength-microamp = <11800>;
> + slew-rate = <1>;
> + };
> +
> + ctrl-pins {
> + pinmux = <RZT2H_PORT_PINMUX(12, 1, 0x29)>, /* SD0_CMD */
> + <RZT2H_PORT_PINMUX(22, 5, 0x29)>; /* SD0_CD */
> + drive-strength-microamp = <9000>;
> + slew-rate = <1>;
> + input-schmitt-disable;
> };
> };
>
> @@ -323,12 +411,49 @@ data-pins {
> <RZT2H_PORT_PINMUX(17, 0, 0x29)>, /* SD1_DATA1 */
> <RZT2H_PORT_PINMUX(17, 1, 0x29)>, /* SD1_DATA2 */
> <RZT2H_PORT_PINMUX(17, 2, 0x29)>; /* SD1_DATA3 */
> + drive-strength-microamp = <5000>;
> + slew-rate = <1>;
> + input-schmitt-disable;
> + };
> +
> + clk-pins {
> + pinmux = <RZT2H_PORT_PINMUX(16, 5, 0x29)>; /* SD1_CLK */
> + drive-strength-microamp = <9000>;
> + slew-rate = <1>;
> + };
> +
> + ctrl-pins {
> + pinmux = <RZT2H_PORT_PINMUX(16, 6, 0x29)>, /* SD1_CMD */
> + <RZT2H_PORT_PINMUX(17, 4, 0x29)>; /* SD1_CD */
> + drive-strength-microamp = <5000>;
> + slew-rate = <1>;
> + input-schmitt-disable;
> + };
> + };
> +
> + sdhi1_pins_uhs: sd1-group-uhs {
> + data-pins {
> + pinmux = <RZT2H_PORT_PINMUX(16, 7, 0x29)>, /* SD1_DATA0 */
> + <RZT2H_PORT_PINMUX(17, 0, 0x29)>, /* SD1_DATA1 */
> + <RZT2H_PORT_PINMUX(17, 1, 0x29)>, /* SD1_DATA2 */
> + <RZT2H_PORT_PINMUX(17, 2, 0x29)>; /* SD1_DATA3 */
> + drive-strength-microamp = <9000>;
> + slew-rate = <1>;
> + input-schmitt-disable;
> + };
> +
> + clk-pins {
> + pinmux = <RZT2H_PORT_PINMUX(16, 5, 0x29)>; /* SD1_CLK */
> + drive-strength-microamp = <11800>;
> + slew-rate = <1>;
> };
>
> ctrl-pins {
> - pinmux = <RZT2H_PORT_PINMUX(16, 5, 0x29)>, /* SD1_CLK */
> - <RZT2H_PORT_PINMUX(16, 6, 0x29)>, /* SD1_CMD */
> + pinmux = <RZT2H_PORT_PINMUX(16, 6, 0x29)>, /* SD1_CMD */
> <RZT2H_PORT_PINMUX(17, 4, 0x29)>; /* SD1_CD */
> + drive-strength-microamp = <9000>;
> + slew-rate = <1>;
> + input-schmitt-disable;
> };
> };
> };
> @@ -342,7 +467,7 @@ &sci0 {
> #if SD0_EMMC
> &sdhi0 {
> pinctrl-0 = <&sdhi0_emmc_pins>;
> - pinctrl-1 = <&sdhi0_emmc_pins>;
> + pinctrl-1 = <&sdhi0_emmc_pins_uhs>;
> pinctrl-names = "default", "state_uhs";
> vmmc-supply = <&reg_3p3v>;
> vqmmc-supply = <&reg_1p8v>;
> @@ -357,7 +482,7 @@ &sdhi0 {
> #if SD0_SD
> &sdhi0 {
> pinctrl-0 = <&sdhi0_sd_pins>;
> - pinctrl-1 = <&sdhi0_sd_pins>;
> + pinctrl-1 = <&sdhi0_sd_pins_uhs>;
> pinctrl-names = "default", "state_uhs";
> vmmc-supply = <&reg_3p3v>;
> vqmmc-supply = <&vqmmc_sdhi0>;
> @@ -372,7 +497,7 @@ &sdhi0 {
> #if SD1_MICRO_SD
> &sdhi1 {
> pinctrl-0 = <&sdhi1_pins>;
> - pinctrl-1 = <&sdhi1_pins>;
> + pinctrl-1 = <&sdhi1_pins_uhs>;
> pinctrl-names = "default", "state_uhs";
> vmmc-supply = <&reg_3p3v>;
> vqmmc-supply = <&vccq_sdhi1>;
> --
> 2.34.1
>
>