[PATCH v2 1/2] arm64: dts: renesas: rzg3l-smarc-som: Enable versa clock generator

[Biju]

From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>

The RZ/G3L SMARC SoM has versa 5P35023B clock generator to generate the
below clocks:
  ref: Not connected
  se1: AUDIO_MCK (11.2896 or 12.2880 MHz)
  se2: RZ_AUDIO_CLK_B (11.2896 MHz)
  se3: RZ_AUDIO_CLK_C (12.2880 MHz)
  diff{1,1B}: ET{0,1}_PHY_CLK (25 MHz)
  diff2{2,2B}: Not connected

Enable versa 5P35023B clock generator on the RZ/G3L SoM DTSI.

Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
v1->v2:
 * Updated commit description with clocks arranged in clock output index
   order.
 * Dropped assigning clock rates of the unused outputs (ref and diff2).
---
 .../boot/dts/renesas/rzg3l-smarc-som.dtsi      | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
index 17bf44778398..5e58e08e7fad 100644
--- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
@@ -40,6 +40,12 @@ memory@48000000 {
 		/* First 128MiB is reserved for secure area. */
 		reg = <0x0 0x48000000 0x0 0x78000000>;
 	};
+
+	x2_clk: x2-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+	};
 };
 
 &eth0 {
@@ -75,6 +81,18 @@ &extal_clk {
 &i2c0 {
 	pinctrl-0 = <&i2c0_pins>;
 	pinctrl-names = "default";
+
+	versa3: clock-generator@68 {
+		compatible = "renesas,5p35023";
+		reg = <0x68>;
+		#clock-cells = <1>;
+		clocks = <&x2_clk>;
+
+		assigned-clocks = <&versa3 1>, <&versa3 2>,
+				  <&versa3 3>, <&versa3 4>;
+		assigned-clock-rates = <12288000>, <11289600>,
+				       <12288000>, <25000000>;
+	};
 };
 
 &mdio0 {
-- 
2.43.0