[PATCH v2 7/7] arm64: dts: renesas: rzg3s-smarc-som: Enable I3C
From: Claudiu Beznea
Date: Thu May 28 2026 - 04:07:12 EST
From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
The Renesas RZ/G3S SMARC SoM board has a connector for I3C interface.
Enable I3C.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
---
Changes in v2:
- dropped pinctrl sleep state
.../boot/dts/renesas/rzg3s-smarc-som.dtsi | 18 ++++++++++++++++++
.../boot/dts/renesas/rzg3s-smarc-switches.h | 4 ++++
2 files changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
index b45acfe6288a..af7357fe4655 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
@@ -168,6 +168,14 @@ a0 80 30 30 9c
};
};
+&i3c {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i3c_pins>;
+ i2c-scl-hz = <400000>;
+ i3c-scl-hz = <12500000>;
+ status = "okay";
+};
+
&pcie_port0 {
clocks = <&versa3 5>;
clock-names = "ref";
@@ -302,6 +310,16 @@ mux {
};
};
+ i3c_pins: i3c {
+ pins = "I3C_SDA", "I3C_SCL";
+#if SW_CONFIG4 == SW_ON
+ power-source = <1200>;
+#else
+ power-source = <1800>;
+#endif
+ input-enable;
+ };
+
sdhi0_pins: sd0 {
data {
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
index bbf908a5322c..9cccc87da057 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
@@ -25,9 +25,13 @@
* @SW_CONFIG3:
* SW_OFF - SD2 is connected to SoC
* SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC
+ * @SW_CONFIG4:
+ * SW_OFF - I3C voltage is 1.8V
+ * SW_ON - I3C voltage is 1.2V
*/
#define SW_CONFIG2 SW_OFF
#define SW_CONFIG3 SW_ON
+#define SW_CONFIG4 SW_OFF
/*
* SW_OPT_MUX[x] switches' states:
--
2.43.0