Re: [PATCH RFC 6/7] spi: spi-mem: Call spi_set_rx_sampling_point() for each op

[Miquel Raynal]

Hello,

>>> Let's say for a worst case scenario a chip has an RX delay of 20ns (the
>>> highest I've seen in datasheets so far is 8ns). In that case the maximum
>>> clock we could safely use for reading the ID would be 1/(2*20e-9) =
>>> 25MHz. Do you think it really makes much of a difference if we read the
>>> ID (only a handful of bytes) at 25MHz or full speed (e. g. 104 MHz)? I
>>> mean this should be fast enough either way, no? But maybe I'm misjudging
>>> this.
>>
>> I am honestly not a big fan of the global penalty, but I am not totally
>> opposed either, especially since you just said you only observed 8ns
>> delays at most. This is 62.5MHz, which is already above what most
>> designs use, so the penalty would be minimal. What about taking this
>> approach and see if that fixes most of our use cases?
>
> What are the actual numbers we are talking about here? I mean, at
> least for SPI NOR, we only read the ID *once*. And it takes about 56
> bits (command + id length of 6). That is about 2us at 25MHz. I'd
> guess the setup and the software handling takes far longer than
> that.

I haven't got the time to resume my SPI NANDs to tests this yet. I
wanted to instrument the code and check the actual impact because we do
several ID reads in SPI NAND. I am still in favour of keeping the
penalty minimal though (see my previous answer) if possible. Frieder,
you are welcome to proceed with a formal follow-up series.

Thanks,
Miquèl