Re: [PATCH 1/2] iommu/arm-smmu-v3: Detect Tegra264 erratum

[Ashish Mhetre]

On 5/28/2026 4:04 PM, Robin Murphy wrote:
> On 2026-05-28 11:16 am, Ashish Mhetre wrote:
> > Tegra264 SMMU is affected by erratum where a TLB entry can survive an
> > invalidation that races with concurrent traffic targeting the same
> > entry. The hardware-recommended software workaround is to issue every
> > CFGI/TLBI command (each followed by CMD_SYNC) twice. The second issue is
> > guaranteed to evict the entry. ATC_INV is not affected and must not be
> > doubled.
> >
> > Add the ARM_SMMU_OPT_TLBI_TWICE option and set it on instances matching
> > the existing "nvidia,tegra264-smmu" compatible. No callers consume the
> > option yet, next patch wires the workaround into the CMDQ issue paths.
>
> Can you not detect this implementation from IIDR like for our other
> workarounds? Otherwise what about ACPI? 

Neither IDR nor IIDR flags this Tegra264-specific bug. We cannot
detect it from any HW register, so we have to rely on the Tegra264
device tree.
Regarding ACPI, the bug is in Tegra264 only, and Tegra264 is
device-tree-only. It doesn't support ACPI/IORT as of now.

Thanks,
Ashish Mhetre