Re: [PATCH v2 1/1] clk: tegra: support 48MHz clock for pll_p_out1

[Thierry Reding]

On Mon, Apr 27, 2026 at 04:24:47PM +0300, Svyatoslav Ryhel wrote:
> From: Dmitry Osipenko <digetx@xxxxxxxxx>
> 
> UEFI on Surface2 sets pll_p_out1 to 48MHz which is not supported by kernel
> and causes BUG() early on. Add 48MHz clock support for pll_p_out1.
> 
> Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx>
> Signed-off-by: Jonas Schwöbel <jonasschwoebel@xxxxxxxx>
> Signed-off-by: Svyatoslav Ryhel <clamor95@xxxxxxxxx>
> ---
>  drivers/clk/tegra/clk-pll.c | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Thierry Reding <treding@xxxxxxxxxx>

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