[PATCH v1 07/12] perf vendor events intel: Update graniterapids events from 1.17 to 1.18
From: Ian Rogers
Date: Fri May 29 2026 - 00:54:18 EST
The updated events and metrics were published in:
https://github.com/intel/perfmon/commit/5b93c8c750300a15b29a9a718511869b280c91f4
Signed-off-by: Ian Rogers <irogers@xxxxxxxxxx>
---
tools/perf/pmu-events/arch/x86/graniterapids/cache.json | 9 +++++++++
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/cache.json b/tools/perf/pmu-events/arch/x86/graniterapids/cache.json
index db28866444b6..95d6b46f3445 100644
--- a/tools/perf/pmu-events/arch/x86/graniterapids/cache.json
+++ b/tools/perf/pmu-events/arch/x86/graniterapids/cache.json
@@ -296,6 +296,15 @@
"SampleAfterValue": "200003",
"UMask": "0x40"
},
+ {
+ "BriefDescription": "Cycles when L1D is locked",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x42",
+ "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
+ "PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x2"
+ },
{
"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)",
"Counter": "0,1,2,3,4,5,6,7",
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index a1548f1306a6..b97d19ae4264 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -13,7 +13,7 @@ GenuineIntel-6-CF,v1.23,emeraldrapids,core
GenuineIntel-6-5[CF],v13,goldmont,core
GenuineIntel-6-7A,v1.01,goldmontplus,core
GenuineIntel-6-B6,v1.12,grandridge,core
-GenuineIntel-6-A[DE],v1.17,graniterapids,core
+GenuineIntel-6-A[DE],v1.18,graniterapids,core
GenuineIntel-6-(3C|45|46),v36,haswell,core
GenuineIntel-6-3F,v29,haswellx,core
GenuineIntel-6-7[DE],v1.24,icelake,core
--
2.54.0.823.g6e5bcc1fc9-goog