Re: [PATCH] riscv: dts: spacemit: k3: Add Ziccrse extension for X100 cores

[Yixun Lan]

Hi Guodong,

On 13:18 Thu 28 May     , Guodong Xu wrote:
> On Tue, May 26, 2026 at 3:23 PM Guodong Xu <guodong@xxxxxxxxxxxx> wrote:
> >
> > Add the Ziccrse ISA extension to all eight X100 cores. Ziccrse
> > provides a forward progress guarantee on LR/SC sequences in main
> > memory regions with cacheability and coherence PMAs.
> >
> > The SpacemiT X100 core supports it per the SpacemiT K3 hardware
> > specification.
> 
> For the record, I have tested this change on SpacemiT K3 Pico-ITX.
> 
> The stress test is run by enabling CONFIG_LOCK_TORTURE_TEST=y then
> boots the kernel with:
> 
>   locktorture.torture_type=spin_lock locktorture.nwriters_stress=16
> 
> driving all 8 harts. It survived sustained torture [ran for ~10 minutes]
> with 0 Fail.
> 
> ... ...
> [  735.588947] torture_spin_lock_write_delay: delay = 25 jiffies.
> [  738.015096] torture_spin_lock_write_delay: delay = 25 jiffies.
> [  739.204713] torture_spin_lock_write_delay: delay = 25 jiffies.
> [  741.195211] Writes:  Total: 714319420  Max/Min: 45946599/43679876   Fail: 0
> 
I appreciate you give more info about the test, just want to make sure,
for the kernel config, the CONFIG_RISCV_TICKET_SPINLOCKS is not enabled?
so it will fall back to use ziccrse implementation..
-- 
Yixun Lan (dlan)