RE: [PATCH v2] arm64: dts: renesas: rzt2h-n2h-evk: Configure eMMC/SDHI pins
From: Fabrizio Castro
Date: Fri May 29 2026 - 05:41:21 EST
Hi Geert,
> From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>
> Sent: 28 May 2026 09:57
> To: Lad, Prabhakar <prabhakar.csengg@xxxxxxxxx>
> Cc: Fabrizio Castro <fabrizio.castro.jz@xxxxxxxxxxx>; magnus.damm <magnus.damm@xxxxxxxxx>; Rob Herring
> <robh@xxxxxxxxxx>; Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>; Conor Dooley <conor+dt@xxxxxxxxxx>; linux-
> renesas-soc@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; Biju Das
> <biju.das.jz@xxxxxxxxxxxxxx>; Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> Subject: Re: [PATCH v2] arm64: dts: renesas: rzt2h-n2h-evk: Configure eMMC/SDHI pins
>
> Hi Prabhakar,
>
> On Wed, 27 May 2026 at 20:06, Lad, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > On Thu, May 14, 2026 at 10:02 PM Fabrizio Castro
> > <fabrizio.castro.jz@xxxxxxxxxxx> wrote:
> > > The HW user manual for the Renesas RZ/T2H and the RZ/N2H states
> > > that for SDR104, SDR50, and HS200 to work properly the eMMC/SDHI
> > > interface pins have to be configured as specified below:
> > > * SDn_CLK pin - drive strength: Ultra High, slew rate: Fast
> > > * Other SDn_* pins: drive strength: High, slew rate: Fast,
> > > Schmitt trigger: disabled (not applicable to SDn_RST pins).
> > >
> > > HS DDR and DDR50 are currently not supported, and for every
> > > other bus mode the eMMC/SDHI interface pins should be configured
> > > as specified below:
> > > * SDn_CLK pin - drive strength: High, slew rate: Fast
> > > * Other SDn_* pins: drive strength: Middle, slew rate: Fast,
> > > Schmitt trigger: disabled (not applicable to SDn_RST pins).
> > >
> > > Adjust the pin definitions accordingly.
> > >
> > > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@xxxxxxxxxxx>
>
> > > --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
> > > @@ -275,12 +275,63 @@ data-pins {
> > > <RZT2H_PORT_PINMUX(12, 7, 0x29)>, /* SD0_DATA5 */
> > > <RZT2H_PORT_PINMUX(13, 0, 0x29)>, /* SD0_DATA6 */
> > > <RZT2H_PORT_PINMUX(13, 1, 0x29)>; /* SD0_DATA7 */
> > > + drive-strength-microamp = <5000>;
> > > + slew-rate = <1>;
> > > + input-schmitt-disable;
> > > };
> > >
> > > - ctrl-pins {
> > > - pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */
> > > - <RZT2H_PORT_PINMUX(12, 1, 0x29)>, /* SD0_CMD */
> > > - <RZT2H_PORT_PINMUX(13, 2, 0x29)>; /* SD0_RST# */
> > > + clk-pins {
> > > + pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>; /* SD0_CLK */
> > > + drive-strength-microamp = <9000>;
> > > + slew-rate = <1>;
> > > + };
> > > +
> > > + cmd-pins {
> > > + pinmux = <RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */
> > > + drive-strength-microamp = <5000>;
> > > + slew-rate = <1>;
> > > + input-schmitt-disable;
> > > + };
> > > +
> > > + rst-pins {
> > > + pinmux = <RZT2H_PORT_PINMUX(13, 2, 0x29)>; /* SD0_RST# */
> > > + drive-strength-microamp = <5000>;
> > > + slew-rate = <1>;
> > > + };
> > > + };
> > > +
> > > + sdhi0_emmc_pins_uhs: sd0-emmc-group-uhs {
> > This needs to be sd0-emmc-uhs-group and to keep it consistent, we can
> > rename sdhi0_emmc_pins_uhs to sdhi0_emmc_uhs_pins (and same for
> > below). Since Geert has already reviewed, perhaps this can be fixed up
> > while applying.
> >
> > Rest LGTM,
> >
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Thanks, will fix that while applying.
Thanks for taking care of this!
Cheers,
Fab
>
> Apparently we've been consistent with using "-group" as a suffix,
> but have a mix of "pins" in the middle and as a suffix.
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds