Re: [PATCH v10 05/31] cxl/mem: Expose dynamic ram A partition in sysfs

From: Anisa Su

Date: Sat May 30 2026 - 03:04:28 EST


On Wed, May 27, 2026 at 04:56:34PM -0700, Dave Jiang wrote:
>
>
> On 5/23/26 2:42 AM, Anisa Su wrote:
> > From: Ira Weiny <ira.weiny@xxxxxxxxx>
> >
> > To properly configure CXL regions user space will need to know the
> > details of the dynamic ram partition.
> >
> > Expose the first dynamic ram partition through sysfs.
> >
> > Signed-off-by: Ira Weiny <ira.weiny@xxxxxxxxx>
> >
> > ---
> > Changes:
> > [anisa: Update kernel version to 7.0]
> > [davidlohr: Remove "persistent" from description of
> > /sys/bus/cxl/devices/memX/dynamic_ram_a/qos_class]
> > ---
> > Documentation/ABI/testing/sysfs-bus-cxl | 24 +++++++++++
> > drivers/cxl/core/memdev.c | 57 +++++++++++++++++++++++++
> > 2 files changed, 81 insertions(+)
> >
> > diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl
> > index 16a9b3d2e2c0..3d95c325f6e0 100644
> > --- a/Documentation/ABI/testing/sysfs-bus-cxl
> > +++ b/Documentation/ABI/testing/sysfs-bus-cxl
> > @@ -89,6 +89,30 @@ Description:
> > and there are platform specific performance related
> > side-effects that may result. First class-id is displayed.
> >
> > +What: /sys/bus/cxl/devices/memX/dynamic_ram_a/size
> > +Date: May, 2025
> > +KernelVersion: v7.0
>
> Probably should update this to 7.3 maybe?
>
Updated
> DJ
>
> > +Contact: linux-cxl@xxxxxxxxxxxxxxx
> > +Description:
> > + (RO) The first Dynamic RAM partition capacity as bytes.
> > +
> > +
> > +What: /sys/bus/cxl/devices/memX/dynamic_ram_a/qos_class
> > +Date: May, 2025
> > +KernelVersion: v7.0
Also updated

Thanks,
Anisa
> > +Contact: linux-cxl@xxxxxxxxxxxxxxx
> > +Description:
> > + (RO) For CXL host platforms that support "QoS Telemmetry"
> > + this attribute conveys a comma delimited list of platform
> > + specific cookies that identifies a QoS performance class
> > + for the partition of the CXL mem device. These
> > + class-ids can be compared against a similar "qos_class"
> > + published for a root decoder. While it is not required
> > + that the endpoints map their local memory-class to a
> > + matching platform class, mismatches are not recommended
> > + and there are platform specific performance related
> > + side-effects that may result. First class-id is displayed.
> > +
> >
> > What: /sys/bus/cxl/devices/memX/serial
> > Date: January, 2022
> > diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
> > index 71602820f896..064cfd628577 100644
> > --- a/drivers/cxl/core/memdev.c
> > +++ b/drivers/cxl/core/memdev.c
> > @@ -101,6 +101,19 @@ static ssize_t pmem_size_show(struct device *dev, struct device_attribute *attr,
> > static struct device_attribute dev_attr_pmem_size =
> > __ATTR(size, 0444, pmem_size_show, NULL);
> >
> > +static ssize_t dynamic_ram_a_size_show(struct device *dev, struct device_attribute *attr,
> > + char *buf)
> > +{
> > + struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
> > + struct cxl_dev_state *cxlds = cxlmd->cxlds;
> > + unsigned long long len = cxl_part_size(cxlds, CXL_PARTMODE_DYNAMIC_RAM_A);
> > +
> > + return sysfs_emit(buf, "%#llx\n", len);
> > +}
> > +
> > +static struct device_attribute dev_attr_dynamic_ram_a_size =
> > + __ATTR(size, 0444, dynamic_ram_a_size_show, NULL);
> > +
> > static ssize_t serial_show(struct device *dev, struct device_attribute *attr,
> > char *buf)
> > {
> > @@ -443,6 +456,25 @@ static struct attribute *cxl_memdev_pmem_attributes[] = {
> > NULL,
> > };
> >
> > +static ssize_t dynamic_ram_a_qos_class_show(struct device *dev,
> > + struct device_attribute *attr, char *buf)
> > +{
> > + struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
> > + struct cxl_dev_state *cxlds = cxlmd->cxlds;
> > +
> > + return sysfs_emit(buf, "%d\n",
> > + part_perf(cxlds, CXL_PARTMODE_DYNAMIC_RAM_A)->qos_class);
> > +}
> > +
> > +static struct device_attribute dev_attr_dynamic_ram_a_qos_class =
> > + __ATTR(qos_class, 0444, dynamic_ram_a_qos_class_show, NULL);
> > +
> > +static struct attribute *cxl_memdev_dynamic_ram_a_attributes[] = {
> > + &dev_attr_dynamic_ram_a_size.attr,
> > + &dev_attr_dynamic_ram_a_qos_class.attr,
> > + NULL,
> > +};
> > +
> > static ssize_t ram_qos_class_show(struct device *dev,
> > struct device_attribute *attr, char *buf)
> > {
> > @@ -519,6 +551,29 @@ static struct attribute_group cxl_memdev_pmem_attribute_group = {
> > .is_visible = cxl_pmem_visible,
> > };
> >
> > +static umode_t cxl_dynamic_ram_a_visible(struct kobject *kobj, struct attribute *a, int n)
> > +{
> > + struct device *dev = kobj_to_dev(kobj);
> > + struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
> > + struct cxl_dpa_perf *perf = part_perf(cxlmd->cxlds, CXL_PARTMODE_DYNAMIC_RAM_A);
> > +
> > + if (a == &dev_attr_dynamic_ram_a_qos_class.attr &&
> > + (!perf || perf->qos_class == CXL_QOS_CLASS_INVALID))
> > + return 0;
> > +
> > + if (a == &dev_attr_dynamic_ram_a_size.attr &&
> > + (!cxl_part_size(cxlmd->cxlds, CXL_PARTMODE_DYNAMIC_RAM_A)))
> > + return 0;
> > +
> > + return a->mode;
> > +}
> > +
> > +static struct attribute_group cxl_memdev_dynamic_ram_a_attribute_group = {
> > + .name = "dynamic_ram_a",
> > + .attrs = cxl_memdev_dynamic_ram_a_attributes,
> > + .is_visible = cxl_dynamic_ram_a_visible,
> > +};
> > +
> > static umode_t cxl_memdev_security_visible(struct kobject *kobj,
> > struct attribute *a, int n)
> > {
> > @@ -547,6 +602,7 @@ static const struct attribute_group *cxl_memdev_attribute_groups[] = {
> > &cxl_memdev_attribute_group,
> > &cxl_memdev_ram_attribute_group,
> > &cxl_memdev_pmem_attribute_group,
> > + &cxl_memdev_dynamic_ram_a_attribute_group,
> > &cxl_memdev_security_attribute_group,
> > NULL,
> > };
> > @@ -555,6 +611,7 @@ void cxl_memdev_update_perf(struct cxl_memdev *cxlmd)
> > {
> > sysfs_update_group(&cxlmd->dev.kobj, &cxl_memdev_ram_attribute_group);
> > sysfs_update_group(&cxlmd->dev.kobj, &cxl_memdev_pmem_attribute_group);
> > + sysfs_update_group(&cxlmd->dev.kobj, &cxl_memdev_dynamic_ram_a_attribute_group);
> > }
> > EXPORT_SYMBOL_NS_GPL(cxl_memdev_update_perf, "CXL");
> >
>