[PATCH 15/17] arm64: dts: renesas: r9a08g046: Add SDHI nodes for RZ/G3L SoC and SDHI1 pincontrol on SMARC EVK

From: Biju

Date: Sat May 30 2026 - 12:11:10 EST

From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>

Add device tree nodes for the three SDHI controllers (SDHI{0,1,2})
on the RZ/G3L SoC (r9a08g046) and enable SDHI1 on the RZ/G3L SMARC
EVK platform with pincontrol and GPIO-based voltage switching
regulator support.

Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 73 ++++++++++++++-
.../boot/dts/renesas/r9a08g046l48-smarc.dts | 88 +++++++++++++++++++
2 files changed, 160 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
index f948ae32f6f5..ce42c945fdf4 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
@@ -762,9 +762,80 @@ dmac: dma-controller@11820000 {
dma-channels = <16>;
};

+ sdhi0: mmc@11c00000 {
+ compatible = "renesas,sdhi-r9a08g046";
+ reg = <0x0 0x11c00000 0 0x10000>;
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A08G046_SDHI0_IMCLK>,
+ <&cpg CPG_MOD R9A08G046_SDHI0_CLK_HS>,
+ <&cpg CPG_MOD R9A08G046_SDHI0_IMCLK2>,
+ <&cpg CPG_MOD R9A08G046_SDHI0_IACLKS>,
+ <&cpg CPG_MOD R9A08G046_SDHI0_IACLKM>;
+ clock-names = "core", "clkh", "cd", "aclk", "aclkm";
+ max-frequency = <150000000>;
+ resets = <&cpg R9A08G046_SDHI0_IXRST>,
+ <&cpg R9A08G046_SDHI0_IXRSTAXIM>,
+ <&cpg R9A08G046_SDHI0_IXRSTAXIS>;
+ reset-names = "rst", "axim", "axis";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
sdhi1: mmc@11c10000 {
+ compatible = "renesas,sdhi-r9a08g046";
reg = <0x0 0x11c10000 0 0x10000>;
- /* placeholder */
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A08G046_SDHI1_IMCLK>,
+ <&cpg CPG_MOD R9A08G046_SDHI1_CLK_HS>,
+ <&cpg CPG_MOD R9A08G046_SDHI1_IMCLK2>,
+ <&cpg CPG_MOD R9A08G046_SDHI1_IACLKS>,
+ <&cpg CPG_MOD R9A08G046_SDHI1_IACLKM>;
+ clock-names = "core", "clkh", "cd", "aclk", "aclkm";
+ max-frequency = <150000000>;
+ resets = <&cpg R9A08G046_SDHI1_IXRST>,
+ <&cpg R9A08G046_SDHI1_IXRSTAXIM>,
+ <&cpg R9A08G046_SDHI1_IXRSTAXIS>;
+ reset-names = "rst", "axim", "axis";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ sdhi1_vqmmc: vqmmc-regulator {
+ regulator-name = "SDHI1-VQMMC";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <1200>;
+ status = "disabled";
+ };
+ };
+
+ sdhi2: mmc@11c20000 {
+ compatible = "renesas,sdhi-r9a08g046";
+ reg = <0x0 0x11c20000 0 0x10000>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A08G046_SDHI2_IMCLK>,
+ <&cpg CPG_MOD R9A08G046_SDHI2_CLK_HS>,
+ <&cpg CPG_MOD R9A08G046_SDHI2_IMCLK2>,
+ <&cpg CPG_MOD R9A08G046_SDHI2_IACLKS>,
+ <&cpg CPG_MOD R9A08G046_SDHI2_IACLKM>;
+ clock-names = "core", "clkh", "cd", "aclk", "aclkm";
+ max-frequency = <150000000>;
+ resets = <&cpg R9A08G046_SDHI2_IXRST>,
+ <&cpg R9A08G046_SDHI2_IXRSTAXIM>,
+ <&cpg R9A08G046_SDHI2_IXRSTAXIS>;
+ reset-names = "rst", "axim", "axis";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ sdhi2_vqmmc: vqmmc-regulator {
+ regulator-name = "SDHI2-VQMMC";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <1200>;
+ status = "disabled";
+ };
};

eth0: ethernet@11c30000 {
diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
index 624fcaea350f..a4cc07408b3f 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
@@ -14,6 +14,7 @@
#define SW_GPIO4 1
#define SW_I3C_EN 0
#define SW_SER0_PMOD 1
+#define SW_SDIO_M2E 0

#define PMOD_GPIO4 0
#define PMOD_GPIO6 0
@@ -38,6 +39,7 @@ / {
aliases {
i2c2 = &i2c2;
i2c3 = &i2c3;
+ mmc1 = &sdhi1;
serial0 = &rsci2;
serial1 = &rsci3;
serial2 = &rsci1;
@@ -69,6 +71,19 @@ codec_dai: codec {
};
};
#endif
+
+#if RZ_BOOT_MODE3
+ vqmmc_sd1_pvdd: regulator-vqmmc-sd1-pvdd {
+ compatible = "regulator-gpio";
+ regulator-name = "SD1_PVDD";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&pinctrl RZG3L_GPIO(J, 1) GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+ states = <3300000 0>, <1800000 1>;
+ regulator-ramp-delay = <1200>;
+ };
+#endif
};

&i2c2 {
@@ -175,6 +190,68 @@ scif0_pins: scif0 {
power-source = <1800>;
};

+#if RZ_BOOT_MODE3
+ sd1-pwr-en-hog {
+ gpio-hog;
+ gpios = <RZG3L_GPIO(J, 2) GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "sd1_pwr_en";
+ };
+#endif
+
+ sdhi1_pins: sd1 {
+ sd1-cd {
+ pinmux = <RZG3L_PORT_PINMUX(J, 0, 8)>; /* SD1_CD */
+ };
+
+ sd1-clk {
+ pinmux = <RZG3L_PORT_PINMUX(G, 0, 1)>; /* SD1_CLK */
+ power-source = <3300>;
+ };
+
+ sd1-cmd {
+ pinmux = <RZG3L_PORT_PINMUX(G, 1, 1)>; /* SD1_CMD */
+ input-enable;
+ power-source = <3300>;
+ bias-pull-up;
+ };
+
+ sd1-data {
+ pinmux = <RZG3L_PORT_PINMUX(G, 2, 1)>, /* SD1_DAT0 */
+ <RZG3L_PORT_PINMUX(G, 3, 1)>, /* SD1_DAT1 */
+ <RZG3L_PORT_PINMUX(G, 4, 1)>, /* SD1_DAT2 */
+ <RZG3L_PORT_PINMUX(G, 5, 1)>; /* SD1_DAT3 */
+ input-enable;
+ power-source = <3300>;
+ };
+ };
+
+ sdhi1_uhs_pins: sd1-uhs {
+ sd1-cd {
+ pinmux = <RZG3L_PORT_PINMUX(J, 0, 8)>; /* SD1_CD */
+ };
+
+ sd1-clk {
+ pinmux = <RZG3L_PORT_PINMUX(G, 0, 1)>; /* SD1_CLK */
+ power-source = <1800>;
+ };
+
+ sd1-cmd {
+ pinmux = <RZG3L_PORT_PINMUX(G, 1, 1)>; /* SD1_CMD */
+ input-enable;
+ power-source = <1800>;
+ };
+
+ sd1-data {
+ pinmux = <RZG3L_PORT_PINMUX(G, 2, 1)>, /* SD1_DAT0 */
+ <RZG3L_PORT_PINMUX(G, 3, 1)>, /* SD1_DAT1 */
+ <RZG3L_PORT_PINMUX(G, 4, 1)>, /* SD1_DAT2 */
+ <RZG3L_PORT_PINMUX(G, 5, 1)>; /* SD1_DAT3 */
+ input-enable;
+ power-source = <1800>;
+ };
+ };
+
ssi0_pins: ssi0 {
pinmux = <RZG3L_PORT_PINMUX(H, 0, 9)>, /* SSIF0_RXD */
<RZG3L_PORT_PINMUX(H, 1, 9)>, /* SSIF0_BCK */
@@ -219,6 +296,17 @@ &scif0 {
pinctrl-names = "default";
};

+#if RZ_BOOT_MODE3
+&sdhi1 {
+ pinctrl-0 = <&sdhi1_pins>;
+ pinctrl-1 = <&sdhi1_uhs_pins>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&reg_3p3v>;
+ vqmmc-supply = <&vqmmc_sd1_pvdd>;
+};
+#endif
+
#if !SW_SD2_EN
&ssi0 {
clocks = <&cpg CPG_MOD R9A08G046_SSI0_PCLK2>,
--
2.43.0