Re: [PATCH v3 3/5] media: qcom: camss: csiphy: Add support for v2.3.0 two-phase CSIPHY
From: bod
Date: Sun May 31 2026 - 04:01:09 EST
On 2026-05-08 02:51 -0700, Hangxiang Ma wrote:
> Add more detailed resource information for CSIPHY devices in the camss
> driver along with the support for v2.3.0 in the 2 phase CSIPHY driver
> that is responsible for the PHY lane register configuration, module
> reset and interrupt handling.
>
> Additionally, generalize the struct name for the lane configuration that
> had been added for Kaanapali and use it for SM8750 as well as they share
> the settings.
>
> Signed-off-by: Hangxiang Ma <hangxiang.ma@xxxxxxxxxxxxxxxx>
Reviewed-by: Bryan O'Donoghue <bod@xxxxxxxxxx>
> ---
> .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 5 +-
> drivers/media/platform/qcom/camss/camss.c | 125 +++++++++++++++++++++
> 2 files changed, 129 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> index c51ffcd93ce1..5b633786314a 100644
> --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> @@ -684,7 +684,7 @@ csiphy_lane_regs lane_regs_sm8650[] = {
> {0x0c10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
> };
>
> -/* 3nm 2PH v 2.4.0 2p5Gbps 4 lane DPHY mode */
> +/* 3nm 2PH v 2.3.0/2.4.0 2p5Gbps 4 lane DPHY mode */
> static const struct
> csiphy_lane_regs lane_regs_2_4_0[] = {
> /* LN 0 */
> @@ -1135,6 +1135,7 @@ static bool csiphy_is_gen2(u32 version)
> case CAMSS_845:
> case CAMSS_8550:
> case CAMSS_8650:
> + case CAMSS_8750:
> case CAMSS_8775P:
> case CAMSS_KAANAPALI:
> case CAMSS_X1E80100:
> @@ -1252,7 +1253,9 @@ static int csiphy_init(struct csiphy_device *csiphy)
> regs->lane_regs = &lane_regs_sa8775p[0];
> regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p);
> break;
> + case CAMSS_8750:
> case CAMSS_KAANAPALI:
> + /* CSPHY v2.4.0 is backward compatible with v2.3.0 settings */
> regs->lane_regs = &lane_regs_2_4_0[0];
> regs->lane_array_size = ARRAY_SIZE(lane_regs_2_4_0);
> regs->offset = 0x1000;
> diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
> index 3cebce812c58..6b7c3160e285 100644
> --- a/drivers/media/platform/qcom/camss/camss.c
> +++ b/drivers/media/platform/qcom/camss/camss.c
> @@ -4238,6 +4238,129 @@ static const struct resources_icc icc_res_sa8775p[] = {
> },
> };
>
> +static const struct camss_subdev_resources csiphy_res_8750[] = {
> + /* CSIPHY0 */
> + {
> + .regulators = {
> + { .supply = "vdd-csiphy0-0p9", .init_load_uA = 148000 },
> + { .supply = "vdd-csiphy0-1p2", .init_load_uA = 14660 }
> + },
> + .clock = { "csiphy0", "csiphy0_timer",
> + "cpas_ahb", "cpas_fast_ahb" },
> + .clock_rate = { { 400000000, 480000000 },
> + { 400000000 },
> + { 0 },
> + { 0 } },
> + .reg = { "csiphy0" },
> + .interrupt = { "csiphy0" },
> + .csiphy = {
> + .id = 0,
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sdm845
> + }
> + },
> + /* CSIPHY1 */
> + {
> + .regulators = {
> + { .supply = "vdd-csiphy1-0p9", .init_load_uA = 148000 },
> + { .supply = "vdd-csiphy1-1p2", .init_load_uA = 14660 }
> + },
> + .clock = { "csiphy1", "csiphy1_timer",
> + "cpas_ahb", "cpas_fast_ahb" },
> + .clock_rate = { { 400000000, 480000000 },
> + { 400000000 },
> + { 0 },
> + { 0 } },
> + .reg = { "csiphy1" },
> + .interrupt = { "csiphy1" },
> + .csiphy = {
> + .id = 1,
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sdm845
> + }
> + },
> + /* CSIPHY2 */
> + {
> + .regulators = {
> + { .supply = "vdd-csiphy2-0p9", .init_load_uA = 148000 },
> + { .supply = "vdd-csiphy2-1p2", .init_load_uA = 14660 }
> + },
> + .clock = { "csiphy2", "csiphy2_timer",
> + "cpas_ahb", "cpas_fast_ahb" },
> + .clock_rate = { { 400000000, 480000000 },
> + { 400000000 },
> + { 0 },
> + { 0 } },
> + .reg = { "csiphy2" },
> + .interrupt = { "csiphy2" },
> + .csiphy = {
> + .id = 2,
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sdm845
> + }
> + },
> + /* CSIPHY3 */
> + {
> + .regulators = {
> + { .supply = "vdd-csiphy3-0p9", .init_load_uA = 148000 },
> + { .supply = "vdd-csiphy3-1p2", .init_load_uA = 14660 }
> + },
> + .clock = { "csiphy3", "csiphy3_timer",
> + "cpas_ahb", "cpas_fast_ahb" },
> + .clock_rate = { { 400000000, 480000000 },
> + { 400000000 },
> + { 0 },
> + { 0 } },
> + .reg = { "csiphy3" },
> + .interrupt = { "csiphy3" },
> + .csiphy = {
> + .id = 3,
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sdm845
> + }
> + },
> + /* CSIPHY4 */
> + {
> + .regulators = {
> + { .supply = "vdd-csiphy4-0p9", .init_load_uA = 148000 },
> + { .supply = "vdd-csiphy4-1p2", .init_load_uA = 14660 }
> + },
> + .clock = { "csiphy4", "csiphy4_timer",
> + "cpas_ahb", "cpas_fast_ahb" },
> + .clock_rate = { { 400000000, 480000000 },
> + { 400000000 },
> + { 0 },
> + { 0 } },
> + .reg = { "csiphy4" },
> + .interrupt = { "csiphy4" },
> + .csiphy = {
> + .id = 4,
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sdm845
> + }
> + },
> + /* CSIPHY5 */
> + {
> + .regulators = {
> + { .supply = "vdd-csiphy5-0p9", .init_load_uA = 148000 },
> + { .supply = "vdd-csiphy5-1p2", .init_load_uA = 14660 }
> + },
> + .clock = { "csiphy5", "csiphy5_timer",
> + "cpas_ahb", "cpas_fast_ahb" },
> + .clock_rate = { { 400000000, 480000000 },
> + { 400000000 },
> + { 0 },
> + { 0 } },
> + .reg = { "csiphy5" },
> + .interrupt = { "csiphy5" },
> + .csiphy = {
> + .id = 5,
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sdm845
> + }
> + },
> +};
> +
> static const struct resources_icc icc_res_sm8750[] = {
> {
> .name = "ahb",
> @@ -5677,7 +5800,9 @@ static const struct camss_resources sm8650_resources = {
> static const struct camss_resources sm8750_resources = {
> .version = CAMSS_8750,
> .pd_name = "top",
> + .csiphy_res = csiphy_res_8750,
> .icc_res = icc_res_sm8750,
> + .csiphy_num = ARRAY_SIZE(csiphy_res_8750),
> .icc_path_num = ARRAY_SIZE(icc_res_sm8750),
> };
>
>
> --
> 2.34.1
>
>