[PATCH v2 0/1 RESEND] clk: tegra: support 48MHz clock for pll_p_out1

[Svyatoslav Ryhel]

UEFI on Surface2 sets pll_p_out1 to 48MHz which is not supported
by kernel and causes BUG() early on. Fix this by adding 48MHz
clock support for pll_p_out1 along with 48MHz support for pll_a,
main pll_p_out1 descendant.

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Changes in v2:
- aligned with downstream 3.4 kernel for tegra114 logic
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Dmitry Osipenko (1):
  clk: tegra: support 48MHz clock for pll_p_out1

 drivers/clk/tegra/clk-pll.c | 1 +
 1 file changed, 1 insertion(+)

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2.51.0