Re: [PATCH v2 phy-next 13/15] dt-bindings: phy: lynx-10g: initial document
From: Alexander Stein
Date: Mon Jun 01 2026 - 03:00:02 EST
Hi,
Am Freitag, 29. Mai 2026, 19:15:07 CEST schrieb Vladimir Oltean:
> Add a schema for the 10G Lynx SerDes. This is very similar to the modern
> form of the 28G Lynx SerDes, which is very much the intention.
>
> We allow both forms of #phy-cells = <1> in the top-level provider
> and #phy-cells = <0> in the per-lane provider for more flexibility to
> consumers, and because the kernel code is shared with the 28G Lynx which
> already has that support for compatibility reasons.
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@xxxxxxx>
> ---
> Cc: devicetree@xxxxxxxxxxxxxxx
> Cc: Conor Dooley <conor+dt@xxxxxxxxxx>
> Cc: Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>
> Cc: Rob Herring <robh@xxxxxxxxxx>
>
> v1->v2:
> - move patch later in series, right before driver
> - deliberately ignoring this Sashiko feedback:
> https://lore.kernel.org/linux-phy/20260529125017.ifqunh52gdzhthdg@skbuf/
> ---
> .../devicetree/bindings/phy/fsl,lynx-10g.yaml | 131 ++++++++++++++++++
> 1 file changed, 131 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml b/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml
> new file mode 100644
> index 000000000000..993f076bba4e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml
> @@ -0,0 +1,131 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/fsl,lynx-10g.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale Lynx 10G SerDes PHY
> +
> +maintainers:
> + - Vladimir Oltean <vladimir.oltean@xxxxxxx>
> +
> +description:
> + The 10G Lynx is a multi-protocol SerDes block which handles networking, PCIe,
> + SATA and other high-speed interfaces. It is present on most QorIQ and
> + Layerscape SoCs. The register map is common, but the integration is
> + SoC-specific, with the differences consisting in register endianness, the
> + number of lanes, protocol converters available per lane and their location in
> + the PCCR registers. Some SoCs have multiple SerDes blocks and those differ in
> + their protocol capabilities per lane.
> +
> +properties:
> + compatible:
> + description:
> + There is intentionally no generic fsl,lynx-10g compatible string due to
> + the hardware inability to report its capabilities, despite having a
> + common register map.
> + enum:
> + - fsl,ls1028a-serdes
> + - fsl,ls1046a-serdes1
> + - fsl,ls1046a-serdes2
> + - fsl,ls1088a-serdes1
> + - fsl,ls1088a-serdes2
> + - fsl,ls2088a-serdes1
> + - fsl,ls2088a-serdes2
Silly question: What about LS1043A? AFAIK it has a single serdes block.
Best regards
Alexander
> +
> + reg:
> + maxItems: 1
> +
> + big-endian: true
> +
> + "#phy-cells":
> + const: 1
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 0
> +
> +patternProperties:
> + "^phy@[0-7]$":
> + type: object
> + description: SerDes lane (single RX/TX differential pair)
> +
> + properties:
> + reg:
> + minimum: 0
> + maximum: 7
> + description: Lane index as seen in register map
> +
> + "#phy-cells":
> + const: 0
> +
> + required:
> + - reg
> + - "#phy-cells"
> +
> + additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - "#phy-cells"
> + - "#address-cells"
> + - "#size-cells"
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - fsl,ls1028a-serdes
> + - fsl,ls1046a-serdes1
> + - fsl,ls1046a-serdes2
> + - fsl,ls1088a-serdes1
> + - fsl,ls1088a-serdes2
> + then:
> + patternProperties:
> + "^phy@[0-7]$":
> + properties:
> + reg:
> + minimum: 0
> + maximum: 3
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + serdes@1ea0000 {
> + compatible = "fsl,ls1028a-serdes";
> + reg = <0x0 0x1ea0000 0x0 0xffff>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #phy-cells = <1>;
> +
> + phy@0 {
> + reg = <0>;
> + #phy-cells = <0>;
> + };
> +
> + phy@1 {
> + reg = <1>;
> + #phy-cells = <0>;
> + };
> +
> + phy@2 {
> + reg = <2>;
> + #phy-cells = <0>;
> + };
> +
> + phy@3 {
> + reg = <3>;
> + #phy-cells = <0>;
> + };
> + };
> + };
>
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