Re: [PATCH v1 9/9] mmc: sdhci-cadence: add Altera Agilex5 SD6HC support

[Kathpalia, Tanmay]

Hi Zach,

Thanks for your feedback.

On 5/28/2026 2:31 AM, Zach Miller wrote:
> On Mon, May 11, 2026 at 01:21:31PM -0700, Tanmay Kathpalia wrote:
> > +static const struct sdhci_ops sdhci_cdns6_agilex5_ops = {
> > +	.set_clock = sdhci_set_clock,
> > +	.get_timeout_clock = sdhci_cdns_get_timeout_clock,
> > +	.set_bus_width = sdhci_set_bus_width,
> > +	.reset = sdhci_reset,
> > +	.platform_execute_tuning = sdhci_cdns_execute_tuning,
> > +	.set_uhs_signaling = sdhci_cdns_set_uhs_signaling,
> > +	.hw_reset = sdhci_cdns6_hw_reset,
> > +	.set_dma_mask = sdhci_cdns_set_dma_mask,
> > +};
> > +
> >   static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = {
> >   	.pltfm_data = {
> >   		.ops = &sdhci_cdns4_ops,
> > @@ -506,6 +544,16 @@ static const struct sdhci_cdns_drv_data sdhci_cdns4_drv_data = {
> >   	},
> >   };
> >   
> > +static const struct sdhci_cdns_drv_data sdhci_cdns6_agilex5_drv_data = {
> > +	.pltfm_data = {
> > +		.ops = &sdhci_cdns6_agilex5_ops,
> > +		.quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
> > +		.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
> > +			   SDHCI_QUIRK2_ACMD23_BROKEN,
> > +	},
> > +	.dma_mask = DMA_BIT_MASK(40),
> > +};
> Would it make sense to add SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN and set
> sdhci_pltfm_clk_get_max_clock() as the get_max_clock() op?
>
> The clock rate that function returns is already the one being overridden
> via sdhci-caps in device tree in patches 3 and 5. Since the
> infrastructure is there, it seems nicer to have this managed by the
> driver rather than requiring users to do it in device tree, especially
> because the clock rate is user-selectable via their FPGA design (so it's
> also a bit different from other caps which may need to be overridden).

Agreed. I've added SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN and wired up
.get_max_clock = sdhci_pltfm_clk_get_max_clock in sdhci_cdns6_agilex5_ops,
so the driver now owns the clock-base handling directly. The sdhci-caps 
clock-base
overrides in both socfpga_agilex5_socdk.dts and 
socfpga_agilex5_socdk_emmc.dts
have been dropped accordingly.

Regards,
Tanmay