[PATCH 0/2] PCI: dwc: custom-arm: reduce bus enumeration latency by ~15%
From: Sumedh Thakre
Date: Mon Jun 01 2026 - 14:02:57 EST
Hi Lorenzo and Bjorn,
I'd like to submit a two-patch series that fixes three independent boot-time
latency regressions in the custom ARM DesignWare PCIe root complex driver and
its companion device tree.
The patches reduce PCIe bus enumeration time by ~15% (7,100 µs mean
improvement across 500 cold-boot cycles) on a Cortex-A55 / DesignWare Gen3 /
NVMe platform:
Root cause | Component | Savings
------------------------------------|-----------|--------
Double PHY reset via .host_init() | Driver | ~8 ms
Sequential PHY + clock init (DTS) | DTS | ~5 ms
1 ms link-up poll on 2–4 ms hw link | Driver | ~2 ms
Baseline: 47,300 µs ±820 µs (n=500)
Patched : 40,200 µs ±610 µs (n=500)
Patch 1/2 adds a phy_initialized guard to prevent double PHY reset and
introduces a platform-specific 250 µs link-up polling interval
(compliant with PCIe Base Spec 4.0 §6.6.1).
Patch 2/2 corrects the device tree to declare explicit PHY clock parents
(enabling parallel probe), adds the required REFCLK stagger margin
(250 ns, fixes sporadic LTSSM failures below 10 °C), and aligns
PERST# assert timing and poll properties with the driver changes.
Both patches are independently bisectable. The series has been tested with:
- 500 cold-boot iteration benchmark (ftrace timestamps)
- dtc validation and dt_binding_check
- dt-validate against dt-schema
- Sparse (make C=1): no new warnings
- checkpatch.pl: 0 errors, 0 warnings
The patches are attached to this email and are also available at:
https://github.com/tsunedh74-droid/linux-pcie-custom-arm-latency-fix/tree/main
I intend these to be queued via the PCI maintainer tree at:
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git
Please let me know if you have any questions, need additional testing data,
or would like me to respin the series.
Thanks for your time and for maintaining the PCI subsystem.
Best regards,
Sumedh Thakre
tsumedh74@xxxxxxxxx
I'd like to submit a two-patch series that fixes three independent boot-time
latency regressions in the custom ARM DesignWare PCIe root complex driver and
its companion device tree.
The patches reduce PCIe bus enumeration time by ~15% (7,100 µs mean
improvement across 500 cold-boot cycles) on a Cortex-A55 / DesignWare Gen3 /
NVMe platform:
Root cause | Component | Savings
------------------------------------|-----------|--------
Double PHY reset via .host_init() | Driver | ~8 ms
Sequential PHY + clock init (DTS) | DTS | ~5 ms
1 ms link-up poll on 2–4 ms hw link | Driver | ~2 ms
Baseline: 47,300 µs ±820 µs (n=500)
Patched : 40,200 µs ±610 µs (n=500)
Patch 1/2 adds a phy_initialized guard to prevent double PHY reset and
introduces a platform-specific 250 µs link-up polling interval
(compliant with PCIe Base Spec 4.0 §6.6.1).
Patch 2/2 corrects the device tree to declare explicit PHY clock parents
(enabling parallel probe), adds the required REFCLK stagger margin
(250 ns, fixes sporadic LTSSM failures below 10 °C), and aligns
PERST# assert timing and poll properties with the driver changes.
Both patches are independently bisectable. The series has been tested with:
- 500 cold-boot iteration benchmark (ftrace timestamps)
- dtc validation and dt_binding_check
- dt-validate against dt-schema
- Sparse (make C=1): no new warnings
- checkpatch.pl: 0 errors, 0 warnings
The patches are attached to this email and are also available at:
https://github.com/tsunedh74-droid/linux-pcie-custom-arm-latency-fix/tree/main
I intend these to be queued via the PCI maintainer tree at:
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git
Please let me know if you have any questions, need additional testing data,
or would like me to respin the series.
Thanks for your time and for maintaining the PCI subsystem.
Best regards,
Sumedh Thakre
tsumedh74@xxxxxxxxx
Attachment:
linux-pcie-custom-arm-latency-fix.zip
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