Re: [PATCH v11 06/22] gpu: nova-core: Blackwell: use correct sysmem flush registers

[John Hubbard]

On 6/1/26 6:13 AM, Alexandre Courbot wrote:
> On Mon Jun 1, 2026 at 4:33 PM JST, Eliot Courtney wrote:
>> On Sat May 30, 2026 at 12:09 PM JST, John Hubbard wrote:
...
>>> +    pub(crate) NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO(u32) @ 0x008a1d58 {
>>> +        31:0    adr => u32;
>>> +    }
>>> +
>>> +    pub(crate) NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI(u32) @ 0x008a1d5c {
>>> +        19:0    adr;
>>> +    }
>>>  }
>>
>> May be nice to move these to the place (HAL) they are used if they
>> aren't used anywhere else (and reduce visibility).
> 
> Indeed, we have a thread on Zulip [1] suggesting to move register
> definitions into subdevice-level `regs.rs` modules. I guess we could
> proactively start doing this with these new registers; on the other
> hand, I'm also fine with keeping the current pattern and doing the move
> later if John prefers to keep things the current way.

I very much want us to focus on making a *serious* attempt at merging
Blackwell support in this kernel cycle.

I emphasize that because moving registers is something that can
*definitely* be done later.


thanks,
-- 
John Hubbard