Re: [PATCH v1 12/26] KVM: arm64: Add PVM_ prefix to avoid name collisions

[Oliver Upton]

On Fri, May 29, 2026 at 05:55:45PM +0200, Steffen Eiden wrote:
> Rename ID_UNALLOCATED to PVM_ID_UNALLOCATED and read_id_reg to
> pvm_read_id_reg to prevent future name collisions with other subsystems.
> While at it, fix whitespace issues in the macro invocations
> 
> Signed-off-by: Steffen Eiden <seiden@xxxxxxxxxxxxx>

No issues with the rename but do you even need the nVHE object at all
for s390?

Thanks,
Oliver

> ---
>  arch/arm64/kvm/hyp/nvhe/sys_regs.c | 48 +++++++++++++++---------------
>  1 file changed, 24 insertions(+), 24 deletions(-)
> 
> diff --git a/arch/arm64/kvm/hyp/nvhe/sys_regs.c b/arch/arm64/kvm/hyp/nvhe/sys_regs.c
> index e8d773d38905..08b14053568b 100644
> --- a/arch/arm64/kvm/hyp/nvhe/sys_regs.c
> +++ b/arch/arm64/kvm/hyp/nvhe/sys_regs.c
> @@ -282,8 +282,8 @@ static void inject_undef64(struct kvm_vcpu *vcpu)
>  	inject_sync64(vcpu, (ESR_ELx_EC_UNKNOWN << ESR_ELx_EC_SHIFT));
>  }
>  
> -static u64 read_id_reg(const struct kvm_vcpu *vcpu,
> -		       struct sys_reg_desc const *r)
> +static u64 pvm_read_id_reg(const struct kvm_vcpu *vcpu,
> +			   struct sys_reg_desc const *r)
>  {
>  	struct kvm *kvm = vcpu->kvm;
>  	u32 reg = reg_to_encoding(r);
> @@ -341,7 +341,7 @@ static bool pvm_access_id_aarch64(struct kvm_vcpu *vcpu,
>  		return false;
>  	}
>  
> -	p->regval = read_id_reg(vcpu, r);
> +	p->regval = pvm_read_id_reg(vcpu, r);
>  	return true;
>  }
>  
> @@ -379,7 +379,7 @@ static bool pvm_idst_access(struct kvm_vcpu *vcpu,
>   * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
>   * (1 <= crm < 8, 0 <= Op2 < 8).
>   */
> -#define ID_UNALLOCATED(crm, op2) {			\
> +#define PVM_ID_UNALLOCATED(crm, op2) {			\
>  	Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2),	\
>  	.access = pvm_access_id_aarch64,		\
>  }
> @@ -438,46 +438,46 @@ static const struct sys_reg_desc pvm_sys_reg_descs[] = {
>  	AARCH32(SYS_MVFR0_EL1),
>  	AARCH32(SYS_MVFR1_EL1),
>  	AARCH32(SYS_MVFR2_EL1),
> -	ID_UNALLOCATED(3,3),
> +	PVM_ID_UNALLOCATED(3, 3),
>  	AARCH32(SYS_ID_PFR2_EL1),
>  	AARCH32(SYS_ID_DFR1_EL1),
>  	AARCH32(SYS_ID_MMFR5_EL1),
> -	ID_UNALLOCATED(3,7),
> +	PVM_ID_UNALLOCATED(3, 7),
>  
>  	/* AArch64 ID registers */
>  	/* CRm=4 */
>  	AARCH64(SYS_ID_AA64PFR0_EL1),
>  	AARCH64(SYS_ID_AA64PFR1_EL1),
>  	AARCH64(SYS_ID_AA64PFR2_EL1),
> -	ID_UNALLOCATED(4,3),
> +	PVM_ID_UNALLOCATED(4, 3),
>  	AARCH64(SYS_ID_AA64ZFR0_EL1),
> -	ID_UNALLOCATED(4,5),
> -	ID_UNALLOCATED(4,6),
> -	ID_UNALLOCATED(4,7),
> +	PVM_ID_UNALLOCATED(4, 5),
> +	PVM_ID_UNALLOCATED(4, 6),
> +	PVM_ID_UNALLOCATED(4, 7),
>  	AARCH64(SYS_ID_AA64DFR0_EL1),
>  	AARCH64(SYS_ID_AA64DFR1_EL1),
> -	ID_UNALLOCATED(5,2),
> -	ID_UNALLOCATED(5,3),
> +	PVM_ID_UNALLOCATED(5, 2),
> +	PVM_ID_UNALLOCATED(5, 3),
>  	AARCH64(SYS_ID_AA64AFR0_EL1),
>  	AARCH64(SYS_ID_AA64AFR1_EL1),
> -	ID_UNALLOCATED(5,6),
> -	ID_UNALLOCATED(5,7),
> +	PVM_ID_UNALLOCATED(5, 6),
> +	PVM_ID_UNALLOCATED(5, 7),
>  	AARCH64(SYS_ID_AA64ISAR0_EL1),
>  	AARCH64(SYS_ID_AA64ISAR1_EL1),
>  	AARCH64(SYS_ID_AA64ISAR2_EL1),
> -	ID_UNALLOCATED(6,3),
> -	ID_UNALLOCATED(6,4),
> -	ID_UNALLOCATED(6,5),
> -	ID_UNALLOCATED(6,6),
> -	ID_UNALLOCATED(6,7),
> +	PVM_ID_UNALLOCATED(6, 3),
> +	PVM_ID_UNALLOCATED(6, 4),
> +	PVM_ID_UNALLOCATED(6, 5),
> +	PVM_ID_UNALLOCATED(6, 6),
> +	PVM_ID_UNALLOCATED(6, 7),
>  	AARCH64(SYS_ID_AA64MMFR0_EL1),
>  	AARCH64(SYS_ID_AA64MMFR1_EL1),
>  	AARCH64(SYS_ID_AA64MMFR2_EL1),
> -	ID_UNALLOCATED(7,3),
> -	ID_UNALLOCATED(7,4),
> -	ID_UNALLOCATED(7,5),
> -	ID_UNALLOCATED(7,6),
> -	ID_UNALLOCATED(7,7),
> +	PVM_ID_UNALLOCATED(7, 3),
> +	PVM_ID_UNALLOCATED(7, 4),
> +	PVM_ID_UNALLOCATED(7, 5),
> +	PVM_ID_UNALLOCATED(7, 6),
> +	PVM_ID_UNALLOCATED(7, 7),
>  
>  	/* Scalable Vector Registers are restricted. */
>  
> -- 
> 2.53.0
>