Re: [PATCH] staging: axis-fifo: remove driver

[Grewstad]

On Wed, Jun 3, 2026 at 2:56 AM Ovidiu Panait
<ovidiu.panait.oss@xxxxxxxxx> wrote:

> I was using this driver to play around with an FPGA board I have (Arty
> Z7-20), so not for commercial purposes. This IP provides a convenient
> way to move data to/from a custom IP in the FPGA. I am using it mostly
> for testing.

Are you still using it?

> I think there are no in-tree users mainly because the IP it talks to
> lives in the FPGA fabric, and drivers for custom FPGA IP blocks
> generally don't get upstreamed.
>
> However, there is the problem of what subsystem this belongs to. It was
> suggested to be turned into a DMA controller to get it moved out of staging:
> https://lore.kernel.org/all/20260227-unboxed-customary-7ce6eda1858c@spud/

This is the main reason i suggested its deletion. it is very difficult to group
it into any particular subsystem because at a low level it is just a
'dumb buffer'. If we do not know its end users and which software uses it,
it will probably be very difficult to move it out of staging.

> Here are people using it and running into issues in Jan 2025.
> https://adaptivesupport.amd.com/s/question/0D54U00008zRBdISAW/vitis-is-not-creating-a-driver-entry-for-axififomm-43?language=zh_CN
> Someone provides a work around:
> https://adaptivesupport.amd.com/s/question/0D54U00008sLBuMSAW/how-to-use-the-axi-stream-fifo-drivers-xllfifoh-xllfifogc-etc-in-the-project?language=en_US
> Then Ovidiu Panait fixed the bug in Sep by adding the correct
> compatible.

There are obviously some users, but in my honest opinion too few,
too minor and too unverified to justify its maintenance in the kernel,
especially because we have no feedback loop for the development of the
driver.

>I ’ve gotten a few emails over the years from people using it, and there is also development happening in parallel on the original github repo:
> https://github.com/jacobfeder/axisfifo

This project has basically ground to a halt now, three commits in 2025 and
basically dead for a year now.

Thanks,
Arihan Bhor


> But I am not sure that this fits as a DMA controller, as it has no DMA
> capabilities. The CPU moves every word individually to and from a register.
>
> My understanding is that the real Xilinx dmaengine IP is
> drivers/dma/xilinx/xilinx_dma.c and this IP is just a simpler, register
> based alternative to move data between the CPU and the FPGA fabric.