RE: [PATCH v17 03/17] pinctrl: renesas: rzg2l: Add SD channel POC support for RZ/G3L

[Biju Das]

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>
> Sent: 04 June 2026 10:33
> Subject: Re: [PATCH v17 03/17] pinctrl: renesas: rzg2l: Add SD channel POC support for RZ/G3L
> 
> Hi Biju,
> 
> On Wed, 3 Jun 2026 at 08:57, Biju <biju.das.au@xxxxxxxxx> wrote:
> > From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> >
> > Add power-on control (POC) support for SD channels 1 and 2 on the
> > RZ/G3L SoC (r9a08g046).
> >
> > Introduce PIN_CFG_IO_VMC_SD2 capability flag (bit 22) and SD_CH2_POC
> > register offset (0x3024). Extend rzg2l_caps_to_pwr_reg() to return
> > SD_CH2_POC when PIN_CFG_IO_VMC_SD2 is set.
> >
> > Replace RZG3L_MPXED_PIN_FUNCS() with RZG2L_MPXED_COMMON_PIN_FUNCS()
> > for port PG and PH pins, dropping PIN_CFG_SOFT_PS which is
> > inappropriate for SD pins, and annotate them with PIN_CFG_IO_VMC_SD1
> > and PIN_CFG_IO_VMC_SD2 respectively.
> >
> > Annotate all RZ/G3L SD0 dedicated pins (CLK, CMD, RST#, DS, DAT0–DAT7)
> > with PIN_CFG_IO_VMC_SD0 so that power-source register lookups work
> > correctly for those pins.
> >
> > Add sd_ch2 field to rzg2l_register_offsets and rzg2l_pinctrl_reg_cache
> > to save and restore the SD_CH2_POC register across suspend/resume cycles.
> >
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> 
> Thanks for your patch!
> 
> > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > @@ -69,6 +69,7 @@
> >  #define PIN_CFG_PVDD1833_OTH_AWO_POC   BIT(19) /* known on RZ/G3L only */
> >  #define PIN_CFG_PVDD1833_OTH_ISO_POC   BIT(20) /* known on RZ/G3L only */
> >  #define PIN_CFG_WDTOVF_N_POC           BIT(21) /* known on RZ/G3L only */
> > +#define PIN_CFG_IO_VMC_SD2             BIT(22) /* known on RZ/G3L only */
> >
> >  #define RZG2L_SINGLE_PIN               BIT_ULL(63)     /* Dedicated pin */
> >  #define RZG2L_VARIABLE_CFG             BIT_ULL(62)     /* Variable cfg for port pins */
> > @@ -258,6 +259,7 @@ static const struct pin_config_item renesas_rzv2h_conf_items[] = {
> >   * @oen: OEN register offset
> >   * @qspi: QSPI register offset
> >   * @other_poc: OTHER_POC register offset
> > + * @sd_ch2: SD_CH2_POC register offset
> >   */
> >  struct rzg2l_register_offsets {
> >         u16 pwpr;
> > @@ -266,6 +268,7 @@ struct rzg2l_register_offsets {
> >         u16 oen;
> >         u16 qspi;
> >         u16 other_poc;
> > +       u16 sd_ch2;
> 
> Nit: your series would cause less conflicts with Claudiu's "[PATCH v3 0/6] pinctrl: renesas: rzg2l:
> Add support for RZ/G3S I3C"
> if you would add sd_ch2 after the existing sd_ch.

OK, will move sd_ch2 after sd_ch.

Cheers,
Biju