Re: [PATCH v2 1/2] arm64: dts: socfpga: Enable the SMMU for SoCFPGA device trees

From: Nazle Asmade, Muhammad Nazim Amirul

Date: Thu Jun 04 2026 - 06:58:38 EST


On 30/5/2026 7:11 pm, Krzysztof Kozlowski wrote:
> [You don't often get email from krzk@xxxxxxxxxx. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> On 15/05/2026 10:00, muhammad.nazim.amirul.nazle.asmade@xxxxxxxxxx wrote:
>> From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@xxxxxxxxxx>
>>
>> Enable the SMMU on the SoCFPGA board device trees where it was
>> missing. The SoC uses a different memory-mapped base address for
>> its peripherals, which requires the System Memory Management Unit
>> (SMMU) to be active so that the Secure Device Manager (SDM) can
>> correctly access those regions through address translation.
>>
>> Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@xxxxxxxxxx>
>> ---
>> Changes in v2:
>> - Move SMMU enable into the base DTSI file instead of individual DTS files
>>
>> arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> index b06c6d5d60ee..64f3739a0c33 100644
>> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> @@ -385,7 +385,7 @@ smmu: iommu@16000000 {
>> interrupt-names = "eventq", "gerror", "priq";
>> dma-coherent;
>> #iommu-cells = <1>;
>> - status = "disabled";
>> + status = "okay";
>
> Which file disabled it?
>
> Best regards,
> Krzysztof
Hi Dinh, Krzysztof

Thank you for the review and feedback!

Addressing Dinh's comment — the commit header has been updated to follow
the subsystem naming convention.

Addressing Krzysztof's question — the SMMU was disabled in
socfpga_agilex5.dtsi itself, where the node is defined with status =
"disabled". This has been clarified in the updated commit message.

https://lore.kernel.org/all/20260604105020.24782-1-muhammad.nazim.amirul.nazle.asmade@xxxxxxxxxx/
https://lore.kernel.org/all/20260604105020.24782-2-muhammad.nazim.amirul.nazle.asmade@xxxxxxxxxx/
https://lore.kernel.org/all/20260604105020.24782-3-muhammad.nazim.amirul.nazle.asmade@xxxxxxxxxx/

BR,
Nazim