Re: [PATCH v4 2/8] clk: renesas: r9a09g047: Add audio clock and reset support

[Geert Uytterhoeven]

Hi John,

On Mon, 25 May 2026 at 13:07, John Madieu <john.madieu.xa@xxxxxxxxxxxxxx> wrote:
> Add clock and reset entries for audio-related modules on the RZ/G3E SoC.
>
> Target modules are:
>  - SSIU (Serial Sound Interface Unit) with SSI ch0-ch9
>  - SCU (Sampling Rate Converter Unit) with SRC ch0-ch9, DVC ch0-ch1,
>    CTU/MIX ch0-ch1
>  - DMACpp (Audio DMA Controller)
>  - ADG (Audio Clock Generator) with divider input clocks and audio
>    master clock outputs
>
> The ADG SSI clock outputs (adg_ssi[0-9]_clk) are parented on
> CLK_PLLCLN_DIV8 as a deliberate simplification: the ADG dynamically
> muxes each output between adg_0_clk_195m and audio_clk[a,b,c] at
> runtime via ADG_AUDIO_CLK_SEL{0,1,2}, owned by the rsnd-adg driver.
>
> While at it, reorder plldty_div16 to group it with the other plldty
> fixed dividers.
>
> Signed-off-by: John Madieu <john.madieu.xa@xxxxxxxxxxxxxx>
> ---
>
> Changes:
>
> v4:
>  - Drop CLK_AUDIO_CLKA and its DEF_INPUT("audio_clka") entry, and
>    reparent adg_0_audio_clka on CLK_AUDIO_EXTAL, since AUDIO_CLKA is
>    provided by the existing AUDIO_EXTAL pin (Geert Uytterhoeven).
>  - Drop the internal core clocks Geert flagged as unused:
>    pllcm33_div4_ddiv2, pllcm33_div4_ddiv2_div2, pllcln_div32,
>    plldty_div2, plldty_div4 and cdiv5_mainosc. pllcln_div4 is kept,
>    as scu_0_clkx2 is parented on it.
>  - Rename the audio module clocks as suggested by Geert: ssif_clk ->
>    ssif_0_clk, scu_clk -> scu_0_clk, scu_clkx2 -> scu_0_clkx2,
>    admac_clk -> dmacpp_0_clk, adg_clks1 -> adg_0_clks1, adg_clk_200m
>    -> adg_0_clk_195m, adg_audio_clk{a,b,c} -> adg_0_audio_clk{a,b,c},
>    ssif_supply_clk -> ssiu_supply_clk. Update the target-module list
>    in the commit message (ADMAC -> DMACpp) to match.
>  - Rename the audio reset entries as suggested by Geert: SCU_RESET_SRU
>    -> SCU_0_RESET_SRU, ADMAC_ARESETN -> DMACpp_0_ARST,
>    ADG_RST_RESET_ADG -> ADG_0_RST_RESET_ADG.
>  - The adg_ssi[0-9]_clk parent is left unchanged as CLK_PLLCLN_DIV8.
>    Geert questioned whether this is correct, since these clocks are
>    ADG-generated. The parent is not changed; instead the commit
>    message now documents that the ADG muxes each output between
>    adg_0_clk_195m and audio_clk[a,b,c] at runtime via
>    ADG_AUDIO_CLK_SEL{0,1,2}, which no static parent can describe.

Thanks for the update!

> --- a/drivers/clk/renesas/r9a09g047-cpg.c
> +++ b/drivers/clk/renesas/r9a09g047-cpg.c

> @@ -532,6 +538,96 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
>                                                 BUS_MSTOP(3, BIT(4))),
>         DEF_MOD("tsu_1_pclk",                   CLK_QEXTAL, 16, 10, 8, 10,
>                                                 BUS_MSTOP(2, BIT(15))),
> +       DEF_MOD("ssif_0_clk",                   CLK_PLLCLN_DIV8, 15, 5, 7, 21,
> +                                               BUS_MSTOP(2, BIT(3) | BIT(4))),

I will reorder while applying, to preserve sort order (by _onindex/_onbit).

Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-clk for v7.3 with the above fixed.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds