Re: [PATCH v2 2/2] PCI: imx6: Assert ref_clk_en after reference clock stabilizes on i.MX95

[Frank Li]

On Mon, May 18, 2026 at 03:27:15PM +0800, Richard Zhu wrote:
> According to the PHY Databook Common Block Signals section, the
> ref_clk_en signal must remain de-asserted until the reference clock is
> running at the appropriate frequency. Once the clock is stable,
> ref_clk_en can be asserted. For lower power states where the reference
> clock to the PHY is disabled, ref_clk_en should also be de-asserted.
>
> Move the ref_clk_en bit manipulation into imx95_pcie_enable_ref_clk()
> to ensure the reference clock stabilizes before ref_clk_en is asserted
> and before the PHY reset is de-asserted. This aligns with the timing
> requirements specified in the PHY documentation.
>
> Fixes: d8574ce57d76 ("PCI: imx6: Add external reference clock input mode support")
> Cc: <stable@xxxxxxxxxxxxxxx>
> Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx>
> ---

Reviewed-by: Frank Li <Frank.Li@xxxxxxx>

>  drivers/pci/controller/dwc/pci-imx6.c | 28 +++++++++++++++++++++------
>  1 file changed, 22 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 66e760015c92..c4b079c93648 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -270,8 +270,6 @@ static int imx95_pcie_init_pre_reset(struct imx_pcie *imx_pcie)
>
>  static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
>  {
> -	bool ext = imx_pcie->enable_ext_refclk;
> -
>  	/*
>  	 * ERR051624: The Controller Without Vaux Cannot Exit L23 Ready
>  	 * Through Beacon or PERST# De-assertion
> @@ -290,10 +288,6 @@ static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
>  			IMX95_PCIE_PHY_CR_PARA_SEL,
>  			IMX95_PCIE_PHY_CR_PARA_SEL);
>
> -	regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0,
> -			   IMX95_PCIE_REF_CLKEN,
> -			   ext ? 0 : IMX95_PCIE_REF_CLKEN);
> -
>  	return 0;
>  }
>
> @@ -742,7 +736,29 @@ static void imx95_pcie_clkreq_override(struct imx_pcie *imx_pcie, bool enable)
>
>  static int imx95_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
>  {
> +	bool ext = imx_pcie->enable_ext_refclk;
> +
>  	imx95_pcie_clkreq_override(imx_pcie, enable);
> +	/*
> +	 * The ref_clk_en signal must remain de-asserted until the
> +	 * reference clock is running at appropriate frequency, at which
> +	 * point this bit can be asserted. For lower power states where
> +	 * the reference clock to the PHY is disabled, it may also be
> +	 * de-asserted.
> +	 * +------------------- -+--------+----------------+
> +	 * | External clock mode | Enable | PCIE_REF_CLKEN |
> +	 * +---------------------+--------+----------------+
> +	 * | TRUE                | X      | 1b'0           |
> +	 * +---------------------+--------+----------------+
> +	 * | FALSE               | TRUE   | 1b'1           |
> +	 * +---------------------+--------+----------------+
> +	 * | FALSE               | FALSE  | 1b'0           |
> +	 * +---------------------+--------+----------------+
> +	 */
> +	regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0,
> +			   IMX95_PCIE_REF_CLKEN,
> +			   ext || !enable ? 0 : IMX95_PCIE_REF_CLKEN);
> +
>  	return 0;
>  }
>
> --
> 2.37.1
>