Re: [PATCH 04/13] gpu: nova-core: falcon: gsp: move PRIV target mask constants

From: Alistair Popple

Date: Tue Jun 16 2026 - 04:02:29 EST


On 2026-06-16 at 00:40 +1000, Eliot Courtney <ecourtney@xxxxxxxxxx> wrote...
> Small cleanup to move these constants which are only used once closer to
> their use location.
>
> Signed-off-by: Eliot Courtney <ecourtney@xxxxxxxxxx>
> ---
> drivers/gpu/nova-core/falcon/gsp.rs | 11 ++++++-----
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/nova-core/falcon/gsp.rs b/drivers/gpu/nova-core/falcon/gsp.rs
> index d1f6f7fcffff..f788b87bd951 100644
> --- a/drivers/gpu/nova-core/falcon/gsp.rs
> +++ b/drivers/gpu/nova-core/falcon/gsp.rs
> @@ -24,10 +24,6 @@
> regs,
> };
>
> -/// Pattern returned by GSP register reads while the PRIV target mask still blocks CPU access.
> -const GSP_TARGET_MASK_LOCKED_PATTERN: u32 = 0xbadf_4100;
> -const GSP_TARGET_MASK_LOCKED_MASK: u32 = 0xffff_ff00;
> -
> /// Type specifying the `Gsp` falcon engine. Cannot be instantiated.
> pub(crate) struct Gsp(());
>
> @@ -70,10 +66,15 @@ pub(crate) fn riscv_branch_privilege_lockdown(&self, bar: Bar0<'_>) -> bool {
>
> /// Returns whether GSP registers can be read by the CPU.
> pub(crate) fn priv_target_mask_released(&self, bar: Bar0<'_>) -> bool {
> + /// Pattern returned by GSP register reads while the PRIV target mask still blocks CPU
> + /// access. The low byte varies; the upper 24 bits are fixed.
> + const LOCKED_PATTERN: u32 = 0xbadf_4100;
> + const LOCKED_MASK: u32 = 0xffff_ff00;

Confirmed this error code doesn't appear to be used more generically across our
driver stack so agree it makes sense to localise it here.

Reviewed-by: Alistair Popple <apopple@xxxxxxxxxx>

> +
> let hwcfg2 = bar
> .read(regs::NV_PFALCON_FALCON_HWCFG2::of::<Gsp>())
> .into_raw();
>
> - hwcfg2 != 0 && (hwcfg2 & GSP_TARGET_MASK_LOCKED_MASK) != GSP_TARGET_MASK_LOCKED_PATTERN
> + hwcfg2 != 0 && (hwcfg2 & LOCKED_MASK) != LOCKED_PATTERN
> }
> }
>
> --
> 2.54.0
>