Re: [PATCH v6 5/8] clk: qcom: tcsrcc-glymur: Add Mahua QREF regulator support

[Konrad Dybcio]

On 6/22/26 7:11 AM, Qiang Yu wrote:
> Mahua is based on Glymur but uses a different QREF topology, requiring
> distinct regulator lists and clock descriptors for its PCIe clock
> references.
> 
> Add mahua-specific regulator arrays and clk descriptor table, and use
> match_data to select the correct descriptor table per compatible string at
> probe time.
> 
> Signed-off-by: Qiang Yu <qiang.yu@xxxxxxxxxxxxxxxx>
> ---

[...]

> +static const struct qcom_clk_ref_desc tcsr_cc_mahua_clk_descs[] = {
> +	[TCSR_EDP_CLKREF_EN] = {
> +		.name = "tcsr_edp_clkref_en",
> +		.offset = 0x60,

EDP goes through CXO1->TX->RPT0->RX0

> +	},
> +	[TCSR_PCIE_2_CLKREF_EN] = {
> +		.name = "tcsr_pcie_2_clkref_en",
> +		.offset = 0x4c,
> +		.regulator_names = mahua_tcsr_tx1_rpt01_rx1_regulators,
> +		.num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt01_rx1_regulators),

this is apparently for PCIE4 (the name you used unfortunately actually
matches the register in TCSR..)

(ok)

> +	},
> +	[TCSR_PCIE_3_CLKREF_EN] = {
> +		.name = "tcsr_pcie_3_clkref_en",
> +		.offset = 0x54,
> +		.regulator_names = mahua_tcsr_tx1_rpt012_rx2_regulators,
> +		.num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt012_rx2_regulators),

This is PCIe3 (actually)

CXO1->TX->RPT0->RPT1->RPT2->RX2 (ok)

> +	},
> +	[TCSR_PCIE_4_CLKREF_EN] = {
> +		.name = "tcsr_pcie_4_clkref_en",
> +		.offset = 0x58,
> +		.regulator_names = mahua_tcsr_tx1_rpt01_rx1_regulators,
> +		.num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt01_rx1_regulators),

This is PCIe6

CXO1->TX->RPT0->RPT1->RX1 (ok)

> +	},
> +	[TCSR_USB2_1_CLKREF_EN] = {
> +		.name = "tcsr_usb2_1_clkref_en",
> +		.offset = 0x6c,
> +	},

(usb_hs phy)
CXO1->TX->RPT3->RPT4->RPT5->RX3

> +	[TCSR_USB2_2_CLKREF_EN] = {
> +		.name = "tcsr_usb2_2_clkref_en",
> +		.offset = 0x70,
> +	},

(mp0 hsphy)
CXO1->TX->RPT3->RPT4->RPT5->RX3

> +	[TCSR_USB2_3_CLKREF_EN] = {
> +		.name = "tcsr_usb2_3_clkref_en",
> +		.offset = 0x74,
> +	},

(mp1 hsphy)
CXO1->TX->RPT3->RPT4->RPT5->RX3


> +	[TCSR_USB2_4_CLKREF_EN] = {
> +		.name = "tcsr_usb2_4_clkref_en",
> +		.offset = 0x88,
> +	},

same as eDP

> +	[TCSR_USB3_0_CLKREF_EN] = {
> +		.name = "tcsr_usb3_0_clkref_en",
> +		.offset = 0x64,
> +	},

(mp0 uniphy)
same as TCSR_USB2_3_CLKREF_EN

> +	[TCSR_USB3_1_CLKREF_EN] = {
> +		.name = "tcsr_usb3_1_clkref_en",
> +		.offset = 0x68,
> +	},

(mp1 uniphy)
same as TCSR_USB2_3_CLKREF_EN

> +	[TCSR_USB4_1_CLKREF_EN] = {
> +		.name = "tcsr_usb4_1_clkref_en",
> +		.offset = 0x44,
> +	},

ok
(although there is a comment suggesting this may be NC..)

> +	[TCSR_USB4_2_CLKREF_EN] = {
> +		.name = "tcsr_usb4_2_clkref_en",
> +		.offset = 0x5c,
> +	},

CXO1->TX->RPT0->RPT1->RX1


You're also missing PCIe_1_CLKREF_EN (+0x48) (for PCIe5)
which goes through CXO1_>TX->RPT0->RPT1->RPT2->RX2

[...]

>  static int tcsr_cc_glymur_probe(struct platform_device *pdev)
>  {
> +	const struct tcsrcc_glymur_data *data = device_get_match_data(&pdev->dev);

Please null-check this

Konrad