Re: [PATCH] clk: qcom: enable ALWAYS_ON for titan_top_gdsc

[Brian Masney]

Hi Jagadeesh,

On Wed, Jul 01, 2026 at 09:37:04AM +0530, Jagadeesh Kona wrote:
> This probably could be due to camcc_gdsc_clk getting turned OFF during the
> sync_state, but this clk is required for GDSC transitions. The camcc_gdsc_clk
> is currently kept always ON from probe in camcc-sc8280xp, but the clock is
> also modeled with clock framework, so the clock can get disabled in sync_state
> callback now.
> 
> Can you please try removing the modelling of camcc_gdsc_clk using below diff
> and see if helps here?
> 
> 
> diff --git a/drivers/clk/qcom/camcc-sc8280xp.c b/drivers/clk/qcom/camcc-sc8280xp.c
> index e97b8d4f3c84..660d8655d391 100644
> --- a/drivers/clk/qcom/camcc-sc8280xp.c
> +++ b/drivers/clk/qcom/camcc-sc8280xp.c
> @@ -1753,24 +1753,6 @@ static struct clk_branch camcc_csiphy3_clk = {
>         },
>  };
> 
> -static struct clk_branch camcc_gdsc_clk = {
> -       .halt_reg = 0xc1e4,
> -       .halt_check = BRANCH_HALT,
> -       .clkr = {
> -               .enable_reg = 0xc1e4,
> -               .enable_mask = BIT(0),
> -               .hw.init = &(struct clk_init_data){
> -                       .name = "camcc_gdsc_clk",
> -                       .parent_hws = (const struct clk_hw*[]){
> -                               &camcc_xo_clk_src.clkr.hw,
> -                       },
> -                       .num_parents = 1,
> -                       .flags = CLK_SET_RATE_PARENT,
> -                       .ops = &clk_branch2_ops,
> -               },
> -       },
> -};
> -
>  static struct clk_branch camcc_icp_ahb_clk = {
>         .halt_reg = 0xc0d8,
>         .halt_check = BRANCH_HALT,
> @@ -2839,7 +2821,6 @@ static struct clk_regmap *camcc_sc8280xp_clocks[] = {
>         [CAMCC_CSIPHY2_CLK] = &camcc_csiphy2_clk.clkr,
>         [CAMCC_CSIPHY3_CLK] = &camcc_csiphy3_clk.clkr,
>         [CAMCC_FAST_AHB_CLK_SRC] = &camcc_fast_ahb_clk_src.clkr,
> -       [CAMCC_GDSC_CLK] = &camcc_gdsc_clk.clkr,
>         [CAMCC_ICP_AHB_CLK] = &camcc_icp_ahb_clk.clkr,
>         [CAMCC_ICP_CLK] = &camcc_icp_clk.clkr,
>         [CAMCC_ICP_CLK_SRC] = &camcc_icp_clk_src.clkr,

So there is the CLK_IGNORE_UNUSED flag that can be added so that we can
keep the clock defined.

diff --git a/drivers/clk/qcom/camcc-sc8280xp.c b/drivers/clk/qcom/camcc-sc8280xp.c
index 18f5a3eb313e1..9a525347fb2a4 100644
--- a/drivers/clk/qcom/camcc-sc8280xp.c
+++ b/drivers/clk/qcom/camcc-sc8280xp.c
@@ -1766,7 +1766,7 @@ static struct clk_branch camcc_gdsc_clk = {
                                &camcc_xo_clk_src.clkr.hw,
                        },
                        .num_parents = 1,
-                       .flags = CLK_SET_RATE_PARENT,
+                       .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
                        .ops = &clk_branch2_ops,
                },
        },

This patch fixes the issue for me. I see that camcc_sc8280xp_probe()
has this:

        /* Keep some clocks always-on */
        qcom_branch_set_clk_en(regmap, 0xc1e4); /* CAMCC_GDSC_CLK */

I'll submit a proper patch for this shortly.

Do you by chance work on the team that deals with clocks at Qualcomm? If
so, it would be really nice if your team could make the time to help
review a patch set that I have to fix some scaling issues with clocks.
Here's some details:

https://lore.kernel.org/linux-clk/akPcgdjlDxd-JmYb@xxxxxxxxxx/

This is two messages up in the same thread that has an example kunit
test snippet showing the problem:
https://lore.kernel.org/linux-clk/CABx5tqK3MymYQZ4owofnzFLnjt+96njw5RG2Vwxo7UJ93A-42g@xxxxxxxxxxxxxx/

Thanks,

Brian