Re: [PATCH 1/2] arm64: dts: renesas: r9a09g057: Add PCIe nodes
From: Geert Uytterhoeven
Date: Wed Jul 01 2026 - 10:31:08 EST
Hi Prabhakar,
On Tue, 2 Jun 2026 at 22:47, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Add PCIe nodes to Renesas RZ/V2H(P) ("R9A09G057") SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Thanks for your patch!
> --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> @@ -1025,6 +1025,146 @@ rsci9: serial@12803000 {
> status = "disabled";
> };
>
> + pcie0: pcie@13400000 {
> + compatible = "renesas,r9a09g057-pcie";
> + reg = <0 0x13400000 0 0x10000>;
> + ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>,
(kast cell) 0x08000000, for better alignment with the next line?
> + <0x43000000 4 0x40000000 4 0x40000000 6 0x00000000>;
> + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 4 0x00000000>;
Sashiko wonders if the first cell should be 0x43000000, as the window
is 16 GiB large, i.e. larger than 4 GiB. I don't know...
If Sashiko is right:
- RZ/G3E is also wrong.
- Should there be a second line for the 32-bit window, covering all
low 4 GiB RAM?
> + pcie1: pcie@13410000 {
> + compatible = "renesas,r9a09g057-pcie";
> + reg = <0 0x13410000 0 0x10000>;
> + ranges = <0x02000000 0 0x38000000 0 0x38000000 0 0x8000000>,
0x0 and 0x080000000, for better alignment with the next line?
> + <0x43000000 0xa 0x40000000 0xa 0x40000000 5 0xc0000000>;
> + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 4 0x00000000>;
Same as above.
The rest LGTM.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds