Re: [PATCH v2 3/4] irqchip/gic-v3: Add Renesas R-Car Gen4 erratum workaround
From: Marek Vasut
Date: Wed Jul 01 2026 - 16:52:35 EST
On 6/21/26 7:00 PM, Marc Zyngier wrote:
Hello Marc,
On Thu, 18 Jun 2026 23:02:01 +0100,I hope this is now addressed in V3.
Marek Vasut <marek.vasut+renesas@xxxxxxxxxxx> wrote:
Renesas R-Car S4/V4H/V4M GIC600 integration has address width for AXI
or APB interface configured to 32 bit, it can therefore access only
the first 4 GiB of physical address space. This information comes from
R-Car V4H Interface Specification sheet, there is currently no technical
update number assigned to this limitation. Further input from hardware
engineer indicates that this limitation also applies to R-Car S4 and V4M.
Name the limitation GEN4GICITS1, and add a driver quirk to mitigate this
limitation.
The quirk is keyed on the combination of the GIC implementation
and the platform identification in the device tree.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
Signed-off-by: Marek Vasut <marek.vasut+renesas@xxxxxxxxxxx>
With the SoB chain issue addressed:
Acked-by: Marc Zyngier <maz@xxxxxxxxxx>