Re: [PATCH v2] PCI: Mask Replay Timer Timeout for Realtek RTS525A

[Max Lee]

On Thu, Jul 02, 2026 at 07:10:46AM +0200, Lukas Wunner wrote:
> It would be good to have full dmesg output for analysis because this
> is all a little murky.

Thanks Mani, Bjorn and Lukas for the detailed analysis.

I collected full boot dmesg and lspci -vv from the affected system.

The system is:

  HP ZBook Power 16 inch G11 Mobile Workstation PC
  BIOS: W97 Ver. 01.09.01, 03/02/2026
  Kernel: 6.17.0-1012-oem

The topology is a direct Root Port -> Endpoint connection, with no switch
in between:

  0000:00:1c.6-[58]----00.0  Realtek RTS525A PCI Express Card Reader

The log shows that OS-native AER is in control:

  acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug SHPCHotplug PME
AER PCIeCapability LTR DPC]
  pcieport 0000:00:1c.6: AER: enabled with IRQ 127

I did not find GHES/HEST/Firmware First AER messages in dmesg/journal for
this boot.

The storm starts after the PCIe port driver enables AER on 0000:00:1c.6
and immediately after rtsx_pci enables the endpoint:

  [    0.798443] pcieport 0000:00:1c.6: AER: enabled with IRQ 127
  [    1.057380] rtsx_pci 0000:58:00.0: enabling device (0000 -> 0002)
  [    1.057399] pcieport 0000:00:1c.6: AER: Correctable error message
received from 0000:58:00.0
  [    1.057405] rtsx_pci 0000:58:00.0: PCIe Bus Error:
severity=Correctable, type=Data Link Layer, (Transmitter ID)
  [    1.057408] rtsx_pci 0000:58:00.0:   device [10ec:525a] error
status/mask=00001000/00006000
  [    1.057411] rtsx_pci 0000:58:00.0:    [12] Timeout

Ratelimiting is present, but the interrupt/callback volume is still very
large:

  [    6.058155] aer_ratelimit: 120541 callbacks suppressed
  [   11.059227] aer_ratelimit: 120906 callbacks suppressed

/proc/interrupts later showed IRQ 127 for 0000:00:1c.6
(PCIe PME, aerdrv, PCIe bwctrl) at 940777 interrupts, while the
endpoint's own rtsx_pci MSI had only 6 interrupts.

Both the endpoint and the immediate upstream port expose AER capability.
On this unpatched boot, Replay Timer Timeout is not masked on either side.

Endpoint 0000:58:00.0:

  Capabilities: [100 v2] Advanced Error Reporting
      CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
      CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+

Root Port 0000:00:1c.6:

  Capabilities: [100 v1] Advanced Error Reporting
      CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
      CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
      RootCmd: CERptEn+ NFERptEn+ FERptEn+
      ErrorSrc: ERR_COR: 5800 ERR_FATAL/NONFATAL: 0000

So for this system, the endpoint does expose AER, and the observed storm
does not require handling the no-endpoint-AER case.

I agree that the v2 wording is imprecise.  pci_mask_replay_timer_timeout()
does not necessarily mask a Root Port; it masks the immediate upstream
Downstream Port leading to pdev, which may be a Root Port or a Switch
Downstream Port.  If I send v3, I will fix the commit log and code comment
to use that wording instead of "parent root port".

I can also include the full dmesg and lspci output if useful.

Thanks,
Max