Re: [PATCH 3/4] arm64: dts: qcom: Add SD Card support for Glymur SoC

[Monish Chunara]

On 6/11/2026 2:34 PM, Konrad Dybcio wrote:
> On 6/10/26 1:15 PM, Monish Chunara wrote:
>> From: Monish Chunara <monish.chunara@xxxxxxxxxxxxxxxx>
>>
>> Add support for SD card on Glymur SoC and enable the required pinctrl
>> configurations.
>>
>> Co-developed-by: Sachin <ssachin@xxxxxxxxxxxxxxxx>
>> Signed-off-by: Sachin <ssachin@xxxxxxxxxxxxxxxx>
> 
> Firstname Lastname?

The mentioned name was the preferred full name of the co-developer.

> 
>> Signed-off-by: Monish Chunara <monish.chunara@xxxxxxxxxxxxxxxx>
>> ---
>>  arch/arm64/boot/dts/qcom/glymur.dtsi | 91 ++++++++++++++++++++++++++++
>>  1 file changed, 91 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
>> index 20b49af7298e..0989fe39e7ef 100644
>> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
>> @@ -3927,6 +3927,57 @@ lpass_ag_noc: interconnect@7e40000 {
>>  			#interconnect-cells = <2>;
>>  		};
>>  
>> +		sdhc_2: mmc@8804000 {
>> +			compatible = "qcom,glymur-sdhci", "qcom,sdhci-msm-v5";
>> +
>> +			reg = <0x0 0x08804000 0x0 0x1000>;
> 
> nit: Let's drop the \n above

ACK, corrected in v2: https://lore.kernel.org/all/20260702094056.3755467-1-mchunara@xxxxxxxxxxxxxxxx/

>> +
>> +			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
>> +			interrupt-names = "hc_irq",
>> +					  "pwr_irq";
>> +
>> +			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
>> +				 <&gcc GCC_SDCC2_APPS_CLK>,
>> +				 <&rpmhcc RPMH_CXO_CLK>;
>> +			clock-names = "iface",
>> +				      "core",
>> +				      "xo";
>> +
>> +			iommus = <&apps_smmu 0xd00 0>;
> 
> '0x0' for the second value as it's a mask, please
> 

ACK, corrected in v2.

>> +			qcom,dll-config = <0x0007442c>;
>> +			qcom,ddr-config = <0x80040868>;
>> +
>> +			power-domains = <&rpmhpd RPMHPD_CX>;
>> +			operating-points-v2 = <&sdhc2_opp_table>;
>> +
>> +			interconnects = <&aggre3_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
>> +					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>> +					<&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
>> +					 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
>> +			interconnect-names = "sdhc-ddr",
>> +					     "cpu-sdhc";
>> +
>> +			bus-width = <4>;
>> +			dma-coherent;
>> +
>> +			status = "disabled";
>> +
>> +			sdhc2_opp_table: opp-table {
>> +				compatible = "operating-points-v2";
>> +
>> +				opp-100000000 {
>> +					opp-hz = /bits/ 64 <100000000>;
>> +					required-opps = <&rpmhpd_opp_low_svs>;
>> +				};
> 
> The SDC doc says this should be 50 MHz> +

Frequencies below 100 MHz would be taken care off by the 100 MHz opp 
entry.

>> +				opp-202000000 {
>> +					opp-hz = /bits/ 64 <202000000>;
>> +					required-opps = <&rpmhpd_opp_svs_l1>;
> 
> And that this should be opp_nom
> 
> But the clock plan doc has info that corresponds with the content of
> your patch, please check which one is correct and file a request for
> fixing the wrong one
> 
> Konrad

This has been checked from the clocks plan PoV and referenced based on 
similar architecture targets. Updated the corners in the v2 series.

Thanks and Regards,
Monish