Re: [PATCH net-next v4 2/2] net: dsa: realtek: rtl8365mb: add HSGMII support for RTL8367S

[Mieczyslaw Nalewaj]

On 7/2/2026 10:47 PM, Johan Alvarado wrote:
> In addition to SGMII, the RTL8367S SerDes also supports HSGMII, which
> carries 2.5 Gbps with the same signaling as SGMII at 2.5x clock rate.
> The chip info table already declares HSGMII as a supported interface
> mode for external interface 1.
> 
> Extend the SerDes PCS to handle HSGMII, which phylink represents as
> 2500base-x:
> 
>  - Select the HSGMII SerDes tuning parameters and external interface
>    mode, and mux the SerDes to MAC8 in HSGMII mode, from pcs_config()
>    according to the interface. The parameters are again lifted from the
>    GPL-licensed Realtek rtl8367c vendor driver, and again only cover
>    the tuning variant for a non-zero chip option, so the mode is gated
>    on the option probed at setup.

[...]

> @@ -1264,6 +1279,16 @@ static int rtl8365mb_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
>  	if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
>  		return -EOPNOTSUPP;
>  
> +	if (interface == PHY_INTERFACE_MODE_2500BASEX) {
> +		sds_jam = rtl8365mb_sds_jam_hsgmii;
> +		sds_jam_size = ARRAY_SIZE(rtl8365mb_sds_jam_hsgmii);
> +		mode = RTL8365MB_EXT_PORT_MODE_HSGMII;
> +	} else {
> +		sds_jam = rtl8365mb_sds_jam_sgmii;
> +		sds_jam_size = ARRAY_SIZE(rtl8365mb_sds_jam_sgmii);
> +		mode = RTL8365MB_EXT_PORT_MODE_SGMII;
> +	}
> +

Johan, looks like you forgot to include the scheduler bandwidth bits for the CPU port. Without this, HSGMII will still be capped at the old SGMII rate limits. Something like:

#define RTL8365MB_REG_INGRESSBW_PORT6_RATE_CTRL1	0x00d0
#define  RTL8365MB_INGRESSBW_PORT6_RATE_CTRL1_INGRESSBW_RATE16_MASK GENMASK(2, 0)

#define RTL8365MB_REG_PORT6_EGRESSBW_CTRL1		0x0399
#define  RTL8365MB_PORT6_EGRESSBW_CTRL1_MASK		GENMASK(2, 0)

#define RTL8365MB_REG_LINE_RATE_HSG_H			0x03fa
#define  RTL8365MB_LINE_RATE_HSG_H_MASK			GENMASK(2, 0)

[...]

		/* Allow full 2.5G on HSGMII CPU port: set scheduler
		 * bandwidth limits to max (0x7). Fixed-link init-only;
		 * no runtime SGMII reconfiguration is expected here.
		 */
		ret = regmap_write(priv->map,
				   RTL8365MB_REG_INGRESSBW_PORT6_RATE_CTRL1,
				   FIELD_PREP(RTL8365MB_INGRESSBW_PORT6_RATE_CTRL1_INGRESSBW_RATE16_MASK,
					      7));
		if (ret)
			return ret;

		ret = regmap_write(priv->map,
				   RTL8365MB_REG_PORT6_EGRESSBW_CTRL1,
				   FIELD_PREP(RTL8365MB_PORT6_EGRESSBW_CTRL1_MASK,
					      7));
		if (ret)
			return ret;

		ret = regmap_write(priv->map,
				   RTL8365MB_REG_LINE_RATE_HSG_H,
				   FIELD_PREP(RTL8365MB_LINE_RATE_HSG_H_MASK,
					      7));
		if (ret)
			return ret;

One more thing while we're on this: I checked the equivalent registers for RGMII on the RTL8367S, and they come out to 1, 1, 7 respectively (INGRESSBW_PORT6_RATE_CTRL1, PORT6_EGRESSBW_CTRL1, LINE_RATE_HSG_H). For correctness these should be set to those values in the RGMII path as well, rather than left at whatever reset/default state they're currently in.