Re: [PATCH v5 09/19] clk: qcom: qcm2290: Set POLL_CFG_GDSCR flag for DISPCC and GPUCC GDSCs

[Dmitry Baryshkov]

On Fri, Jul 03, 2026 at 12:01:31AM +0530, Imran Shaik wrote:
> On some targets, the GDSCR status bit may not reflect the actual state of

Which targets? This is all about Agatti.

> the GDSC, instead the power on/off bits in CFG_GDSCR must be polled to
> determine the GDSC state correctly. Set POLL_CFG_GDSCR flag for the QCM2290
> MDSS GDSC and GPUCC GX GDSC to ensure the correct GDSC status. This is not
> applicable for GPUCC CX GDSC, which relies on gds_hw_ctrl status.
> 
> Signed-off-by: Imran Shaik <imran.shaik@xxxxxxxxxxxxxxxx>
> ---
>  drivers/clk/qcom/dispcc-qcm2290.c | 2 +-
>  drivers/clk/qcom/gpucc-qcm2290.c  | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c
> index 89a6cdd26217381cd44a515766363cf94d0aaeeb..6ee074555099ab72106cfae7c21adbd1b4a0fdac 100644
> --- a/drivers/clk/qcom/dispcc-qcm2290.c
> +++ b/drivers/clk/qcom/dispcc-qcm2290.c
> @@ -467,7 +467,7 @@ static struct gdsc mdss_gdsc = {
>  		.name = "mdss_gdsc",
>  	},
>  	.pwrsts = PWRSTS_OFF_ON,
> -	.flags = HW_CTRL_TRIGGER,
> +	.flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR,
>  };
>  
>  static struct gdsc *disp_cc_qcm2290_gdscs[] = {
> diff --git a/drivers/clk/qcom/gpucc-qcm2290.c b/drivers/clk/qcom/gpucc-qcm2290.c
> index 66dea9d2a0e519dfc64d977ef107b5c875da3869..3b130f69bb93898ce49654f2366851a7c1c94524 100644
> --- a/drivers/clk/qcom/gpucc-qcm2290.c
> +++ b/drivers/clk/qcom/gpucc-qcm2290.c
> @@ -313,7 +313,7 @@ static struct gdsc gpu_gx_gdsc = {
>  	},
>  	.parent = &gpu_cx_gdsc.pd,
>  	.pwrsts = PWRSTS_OFF_ON,
> -	.flags = CLAMP_IO | AON_RESET | SW_RESET,
> +	.flags = POLL_CFG_GDSCR | CLAMP_IO | AON_RESET | SW_RESET,
>  };
>  
>  static struct clk_regmap *gpu_cc_qcm2290_clocks[] = {
> 
> -- 
> 2.34.1
> 

-- 
With best wishes
Dmitry