Re: [PATCH v3 RESEND 2/5] arm64: dts: qcom: Add device tree for Nord SoC series

[Shawn Guo]

On Tue, Jun 16, 2026 at 12:57:42PM +0200, Konrad Dybcio wrote:
> On 5/26/26 7:12 AM, Shawn Guo wrote:
> > Add base device tree include (nord.dtsi) for the Nord SoC series
> > describing the core hardware components:
> > 
> >  - 18 Oryon (qcom,oryon-1-5) cores in three clusters, with PSCI-based
> >    power management and CPU/cluster idle states
> >  - ARM GICv3 interrupt controller with ITS
> >  - TLMM GPIO/pinctrl controller
> >  - 8 TSENS thermal sensors with thermal zones
> >  - 3 APPS SMMU-500 instances
> >  - 3 QUPv3 GENI SE QUP blocks
> >  - PDP SCMI channel and mailbox
> >  - Watchdog, TRNG and TCSR
> >  - Reserved memory, CMD-DB and firmware SCM
> >  - PSCI and architected timers
> 
> [...]
> 
> > +		dump_mem: mem-dump-region {
> > +			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
> 
> off-by-1?

Yes. We have the same thing in sdm845.dtsi and sm8750.dtsi. Unless you
think that missing the last byte is functionally problematic, I would
rather be consistent with the established pattern in the tree.

> 
> [...]
> 
> > +		intc: interrupt-controller@17000000 {
> > +			compatible = "arm,gic-v3";
> > +			reg = <0x0 0x17000000 0x0 0x10000>,     /* GICD */
> > +			      <0x0 0x17080000 0x0 0x480000>;    /* GICR * 18 */
> 
> Please drop these comments

Sure!

> Otherwise looks alright
> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>

Thank you for the review, Konrad!

Shawn