[PATCH] arm64: dts: qcom: glymur: add CPU capacity-dmips-mhz
From: Pradyot Kumar Nayak
Date: Mon Jul 06 2026 - 03:55:15 EST
The Glymur SoC has two distinct core types within the same Oryon
microarchitecture generation:
- qcom,oryon-2-2 (cpu0-cpu5, cluster 0)
- qcom,oryon-2-1 (cpu6-cpu11, cluster 1; cpu12-cpu17, cluster 2)
Without capacity-dmips-mhz the Energy Aware Scheduler treats all 18
cores as equal, leading to suboptimal task placement and frequency
selection. In particular, heavy tasks may be pinned to cluster 0 driving
them to maximum frequency/voltage while cluster 1/2 sit idle.
Fix this by using distinct capacity-dmips-mhz numbers.
Values are derived from DPC (DMIPS-per-clock) measurements at the
825.6 MHz nominal operating point:
oryon-2-2: 1024 (normalised baseline)
oryon-2-1: 1372 (ratio ~1.34x vs oryon-2-2)
Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/glymur.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index 20b49af7298e..1b5b2ed93767 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -39,6 +39,7 @@ cpu0: cpu@0 {
compatible = "qcom,oryon-2-2";
reg = <0x0 0x0>;
enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
power-domains = <&cpu_pd0>, <&scmi_perf 0>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_0>;
@@ -56,6 +57,7 @@ cpu1: cpu@100 {
compatible = "qcom,oryon-2-2";
reg = <0x0 0x100>;
enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
power-domains = <&cpu_pd1>, <&scmi_perf 0>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_0>;
@@ -67,6 +69,7 @@ cpu2: cpu@200 {
compatible = "qcom,oryon-2-2";
reg = <0x0 0x200>;
enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
power-domains = <&cpu_pd2>, <&scmi_perf 0>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_0>;
@@ -78,6 +81,7 @@ cpu3: cpu@300 {
compatible = "qcom,oryon-2-2";
reg = <0x0 0x300>;
enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
power-domains = <&cpu_pd3>, <&scmi_perf 0>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_0>;
@@ -89,6 +93,7 @@ cpu4: cpu@400 {
compatible = "qcom,oryon-2-2";
reg = <0x0 0x400>;
enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
power-domains = <&cpu_pd4>, <&scmi_perf 0>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_0>;
@@ -100,6 +105,7 @@ cpu5: cpu@500 {
compatible = "qcom,oryon-2-2";
reg = <0x0 0x500>;
enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
power-domains = <&cpu_pd5>, <&scmi_perf 0>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_0>;
@@ -111,6 +117,7 @@ cpu6: cpu@10000 {
compatible = "qcom,oryon-2-1";
reg = <0x0 0x10000>;
enable-method = "psci";
+ capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd6>, <&scmi_perf 1>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_1>;
@@ -128,6 +135,7 @@ cpu7: cpu@10100 {
compatible = "qcom,oryon-2-1";
reg = <0x0 0x10100>;
enable-method = "psci";
+ capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd7>, <&scmi_perf 1>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_1>;
@@ -139,6 +147,7 @@ cpu8: cpu@10200 {
compatible = "qcom,oryon-2-1";
reg = <0x0 0x10200>;
enable-method = "psci";
+ capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd8>, <&scmi_perf 1>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_1>;
@@ -150,6 +159,7 @@ cpu9: cpu@10300 {
compatible = "qcom,oryon-2-1";
reg = <0x0 0x10300>;
enable-method = "psci";
+ capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd9>, <&scmi_perf 1>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_1>;
@@ -161,6 +171,7 @@ cpu10: cpu@10400 {
compatible = "qcom,oryon-2-1";
reg = <0x0 0x10400>;
enable-method = "psci";
+ capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd10>, <&scmi_perf 1>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_1>;
@@ -172,6 +183,7 @@ cpu11: cpu@10500 {
compatible = "qcom,oryon-2-1";
reg = <0x0 0x10500>;
enable-method = "psci";
+ capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd11>, <&scmi_perf 1>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_1>;
@@ -183,6 +195,7 @@ cpu12: cpu@20000 {
compatible = "qcom,oryon-2-1";
reg = <0x0 0x20000>;
enable-method = "psci";
+ capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd12>, <&scmi_perf 2>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_2>;
@@ -200,6 +213,7 @@ cpu13: cpu@20100 {
compatible = "qcom,oryon-2-1";
reg = <0x0 0x20100>;
enable-method = "psci";
+ capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd13>, <&scmi_perf 2>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_2>;
@@ -211,6 +225,7 @@ cpu14: cpu@20200 {
compatible = "qcom,oryon-2-1";
reg = <0x0 0x20200>;
enable-method = "psci";
+ capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd14>, <&scmi_perf 2>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_2>;
@@ -222,6 +237,7 @@ cpu15: cpu@20300 {
compatible = "qcom,oryon-2-1";
reg = <0x0 0x20300>;
enable-method = "psci";
+ capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd15>, <&scmi_perf 2>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_2>;
@@ -233,6 +249,7 @@ cpu16: cpu@20400 {
compatible = "qcom,oryon-2-1";
reg = <0x0 0x20400>;
enable-method = "psci";
+ capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd16>, <&scmi_perf 2>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_2>;
@@ -244,6 +261,7 @@ cpu17: cpu@20500 {
compatible = "qcom,oryon-2-1";
reg = <0x0 0x20500>;
enable-method = "psci";
+ capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd17>, <&scmi_perf 2>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_2>;
---
base-commit: be5c93fa674f0fc3c8f359c2143abce6bbb422e6
change-id: 20260703-add-cpu-capacity-dmips-mhz-2095d25c411e
Best regards,
--
Pradyot Kumar Nayak <pradyot.nayak@xxxxxxxxxxxxxxxx>