Re: [PATCH v2 4/6] clk: qcom: Add Nord display clock controller support

[Alexandre Mergnat]

On Tue, 21 Jul 2026 12:37:19 +0530, Taniya Das <taniya.das@xxxxxxxxxxxxxxxx> wrote:

Hi Taniya Das,

>
> diff --git a/drivers/clk/qcom/dispcc0-nord.c b/drivers/clk/qcom/dispcc0-nord.c
> new file mode 100644
> index 000000000000..6d9c74ffe9a1
> --- /dev/null
> +++ b/drivers/clk/qcom/dispcc0-nord.c
> @@ -0,0 +1,2004 @@
> [ ... skip 1944 lines ... ]
> +	&mdss_0_disp_cc_pll3,
> +};
> +
> +static const u32 disp_cc_0_nord_critical_cbcrs[] = {
> +	0xc00c, /* MDSS_DISP_CC_AHB_CLK */
> +	0xc008, /* MDSS_DISP_CC_VSYNC_CLK */

These two comments look mislabeled: offsets 0xc00c/0xc008 are the RSCC AHB/VSYNC
clocks (cf. disp_cc_mdss_rscc_ahb_clk @0xc00c and disp_cc_mdss_rscc_vsync_clk @0xc008
in dispcc-sm8550.c / dispcc-milos.c), whereas the plain AHB/VSYNC branches in this
file are at 0x80c0 / 0x8030. dispcc1-nord.c labels these same offsets as RSCC.
Can you double check and update them to MDSS_DISP_CC_RSCC_AHB_CLK and
MDSS_DISP_CC_RSCC_VSYNC_CLK ?
The offsets looks correct, only the comments differ.

>
> diff --git a/drivers/clk/qcom/dispcc1-nord.c b/drivers/clk/qcom/dispcc1-nord.c
> new file mode 100644
> index 000000000000..6b4efa735b9e
> --- /dev/null
> +++ b/drivers/clk/qcom/dispcc1-nord.c
> @@ -0,0 +1,2004 @@
> [ ... skip 1944 lines ... ]
> +	&mdss_1_disp_cc_pll3,
> +};
> +
> +static const u32 disp_cc_1_nord_critical_cbcrs[] = {
> +	0xc00c, /* MDSS_DISP_CC_RSCC_AHB_CLK */
> +	0xc008, /* MDSS_DISP_CC_RSCC_VSYNC CLK */

MDSS_DISP_CC_RSCC_VSYNC_CLK to match the other entries.

Minor: "MDSS_DISP_CC_RSCC_VSYNC CLK" is missing an underscore, should be

Minor: "MDSS_DISP_CC_RSCC_VSYNC CLK" is missing an underscore, should be

-- 
Alexandre Mergnat <amergnat@xxxxxxxxxxxx>