[PATCH 1/2] dt-bindings: clock: qcom: Add Hawi GPU clock controllers
From: Dongfang Zhao
Date: Mon Jul 27 2026 - 01:50:44 EST
Add the device tree binding and clock, reset and power-domain IDs for the
Hawi graphics clock controller. This lets Hawi device trees describe the
GPU clocks, resets and power domains, and lets dtbs_check validate those
nodes.
Add the qcom,hawi-gxclkctl compatible for the Hawi GX clock controller,
using qcom,kaanapali-gxclkctl as the fallback because the register layout
is identical.
Signed-off-by: Dongfang Zhao <dongfang.zhao@xxxxxxxxxxxxxxxx>
---
.../devicetree/bindings/clock/qcom,hawi-gpucc.yaml | 78 ++++++++++++++++++++++
.../bindings/clock/qcom,kaanapali-gxclkctl.yaml | 22 +++---
include/dt-bindings/clock/qcom,hawi-gpucc.h | 47 +++++++++++++
3 files changed, 139 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,hawi-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,hawi-gpucc.yaml
new file mode 100644
index 000000000000..3ba6e4d212ed
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,hawi-gpucc.yaml
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,hawi-gpucc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Graphics Clock & Reset Controller on Hawi
+
+maintainers:
+ - Dongfang Zhao <dongfang.zhao@xxxxxxxxxxxxxxxx>
+
+description: |
+ Qualcomm graphics clock control module provides the clocks, resets and power
+ domains on Qualcomm SoCs.
+
+ See also: include/dt-bindings/clock/qcom,hawi-gpucc.h
+
+properties:
+ compatible:
+ const: qcom,hawi-gpucc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: GPLL0 main branch source
+ - description: GPLL0 div branch source
+
+ power-domains:
+ items:
+ - description: A phandle to the CX power-domain
+ - description: A phandle to the MX power-domain
+ - description: A phandle to the GMXC power-domain
+
+ required-opps:
+ items:
+ - description: A phandle to an OPP node describing CX performance points
+ - description: A phandle to an OPP node describing MX performance points
+ - description: A phandle to an OPP node describing GMXC performance points
+
+required:
+ - compatible
+ - clocks
+ - power-domains
+ - required-opps
+ - '#power-domain-cells'
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,hawi-gcc.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clock-controller@3d90000 {
+ compatible = "qcom,hawi-gpucc";
+ reg = <0x0 0x03d90000 0x0 0x9800>;
+ clocks = <&bi_tcxo_div2>,
+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MX>,
+ <&rpmhpd RPMHPD_GMXC>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs_d3>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml b/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml
index e868963f659b..28b653f6b64d 100644
--- a/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml
@@ -4,25 +4,31 @@
$id: http://devicetree.org/schemas/clock/qcom,kaanapali-gxclkctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm Graphics power domain Controller on Kaanapali
+title: Qualcomm Graphics GX Power Domain Controller
maintainers:
- Taniya Das <taniya.das@xxxxxxxxxxxxxxxx>
description: |
- Qualcomm GX(graphics) is a clock controller which has PLLs, clocks and
- Power domains (GDSC). This module provides the power domains control
- of gxclkctl on Qualcomm SoCs which helps the recovery of Graphics subsystem.
+ The Qualcomm graphics GX clock controller (GXCLKCTL) contains PLLs, clocks
+ and power domains (GDSC). This module provides the power domain control of
+ GXCLKCTL on Qualcomm SoCs, which helps the recovery of the graphics
+ subsystem.
See also:
include/dt-bindings/clock/qcom,kaanapali-gxclkctl.h
properties:
compatible:
- enum:
- - qcom,glymur-gxclkctl
- - qcom,kaanapali-gxclkctl
- - qcom,sm8750-gxclkctl
+ oneOf:
+ - enum:
+ - qcom,glymur-gxclkctl
+ - qcom,kaanapali-gxclkctl
+ - qcom,sm8750-gxclkctl
+ - items:
+ - enum:
+ - qcom,hawi-gxclkctl
+ - const: qcom,kaanapali-gxclkctl
power-domains:
description:
diff --git a/include/dt-bindings/clock/qcom,hawi-gpucc.h b/include/dt-bindings/clock/qcom,hawi-gpucc.h
new file mode 100644
index 000000000000..181534771b10
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,hawi-gpucc.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_HAWI_H
+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_HAWI_H
+
+/* GPU_CC clocks */
+#define GPU_CC_AHB_CLK 0
+#define GPU_CC_CB_CLK 1
+#define GPU_CC_CX_ACCU_SHIFT_CLK 2
+#define GPU_CC_CX_GMU_CLK 3
+#define GPU_CC_CXO_AON_CLK 4
+#define GPU_CC_CXO_CLK 5
+#define GPU_CC_DEMET_CLK 6
+#define GPU_CC_DPM_CLK 7
+#define GPU_CC_FREQ_MEASURE_CLK 8
+#define GPU_CC_GMU_CLK_SRC 9
+#define GPU_CC_GPU_SMMU_VOTE_CLK 10
+#define GPU_CC_GX_ACCU_SHIFT_CLK 11
+#define GPU_CC_HUB_AON_CLK 12
+#define GPU_CC_HUB_CLK_SRC 13
+#define GPU_CC_HUB_CX_INT_CLK 14
+#define GPU_CC_HUB_DIV_CLK_SRC 15
+#define GPU_CC_MEMNOC_GFX_CLK 16
+#define GPU_CC_MXG_AHB_CLK 17
+#define GPU_CC_MXG_XO_CLK 18
+#define GPU_CC_PLL0 19
+#define GPU_CC_RSCC_HUB_AON_CLK 20
+#define GPU_CC_RSCC_XO_AON_CLK 21
+#define GPU_CC_SLEEP_CLK 22
+
+/* GPU_CC power domains */
+#define GPU_CC_CX_GDSC 0
+#define GPU_CC_MXG_GDSC 1
+
+/* GPU_CC resets */
+#define GPU_CC_CB_BCR 0
+#define GPU_CC_CX_BCR 1
+#define GPU_CC_FAST_HUB_BCR 2
+#define GPU_CC_GMU_BCR 3
+#define GPU_CC_GX_BCR 4
+#define GPU_CC_MXG_BCR 5
+#define GPU_CC_XO_BCR 6
+
+#endif
--
2.43.0