Re: [PATCH 1/2] dt-bindings: mailbox: add Axiado AX3005 mailbox

[Krzysztof Kozlowski]

On 30/07/2026 06:36, Swark Yang wrote:

> +  - Krishnakumar Kesavan <kkesavan@xxxxxxxxxx>
> +  - Prasad Bolisetty <pbolisetty@xxxxxxxxxx>
> +  - Swark Yang <syang@xxxxxxxxxx>
> +
> +description: |

Do not need '|' unless you need to preserve formatting.

> +  The Axiado mailbox controller provides inter-processor communication
> +  channels between subsystems within the Axiado SoC. The hardware has
> +  separate TX and RX register regions. Only the RX channels (channels 8-15)
> +  generate interrupts; TX channels are purely poll/write-based.
> +
> +properties:
> +  compatible:
> +    const: axiado,ax3005-mailbox
> +
> +  reg:
> +    items:
> +      - description: TX mailbox register region
> +      - description: RX mailbox register region
> +
> +  reg-names:
> +    items:
> +      - const: tx
> +      - const: rx
> +
> +  interrupts:
> +    description: |

Do not need '|' unless you need to preserve formatting.

> +      One interrupt per RX channel. The hardware exposes eight RX interrupt
> +      lines corresponding to channels 8 through 15.
> +    minItems: 8

Drop


> +            reg-names = "tx", "rx";
> +            /* Only RX channels (8-15) have IRQs */
> +            interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
> +            interrupt-names = "ch8", "ch9", "ch10", "ch11",
> +                              "ch12", "ch13", "ch14", "ch15";
> +            interrupt-parent = <&gic500>;
> +            #mbox-cells = <1>;
> +            status = "okay";

Drop


Best regards,
Krzysztof