[PATCH] x86/mce: Set up the polling timer before CMCI discovery

From: Breno Leitao

Date: Mon Aug 03 2026 - 05:58:10 EST


I hit the following on one of my machines:

mce: CPU0 BANK15 CMCI inherited storm
------------[ cut here ]------------
ODEBUG: assert_init not available (active state 0) object: (____ptrval____) object type: timer_list hint: 0x0
WARNING: lib/debugobjects.c:632 at debug_object_assert_init+0x178/0x230, CPU#0: swapper/0/0
CPU: 0 UID: 0 PID: 0 Comm: swapper/0 Not tainted 7.2.0-rc5 #3 PREEMPTLAZY
RIP: 0010:debug_object_assert_init+0x18f/0x230
Call Trace:
<TASK>
__mod_timer
mce_timer_kick
cmci_discover
intel_init_cmci
mce_intel_feature_init
mcheck_cpu_init
identify_cpu
identify_boot_cpu
arch_cpu_finalize_init
start_kernel

A second splat follows right after, from timer_setup() finding that same
timer already queued:

ODEBUG: init active (active state 0) object: (____ptrval____) object type: timer_list hint: stub_timer+0x0/0x10

This is happening because we are trying to modify the timer before it
was properly setup'ed.

Set the timer up first. __mcheck_cpu_setup_timer() only calls
timer_setup(), and depends on neither the generic nor the vendor init.

Fixes: 1f68ce2a0272 ("x86/mce: Handle Intel threshold interrupt storms")
Cc: stable@xxxxxxxxxxxxxxx
Signed-off-by: Breno Leitao <leitao@xxxxxxxxxx>
---
arch/x86/kernel/cpu/mce/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 9bba1e2f03af7..cfb74be19994d 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -2266,10 +2266,10 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c)

mca_cfg.initialized = 1;

+ __mcheck_cpu_setup_timer();
__mcheck_cpu_init_generic();
__mcheck_cpu_init_vendor(c);
__mcheck_cpu_init_prepare_banks();
- __mcheck_cpu_setup_timer();
cr4_set_bits(X86_CR4_MCE);
}


---
base-commit: 8ba098e6b6ff0db8edf28528d1552be261af30d4
change-id: 20260731-mce_timer_init-ab3148a08961

Best regards,
--
Breno Leitao <leitao@xxxxxxxxxx>