Re: [PATCH v5 11/25] clk: mediatek: pll: Factorise pll power on/off sequences

[Brian Masney]

On Sat, Aug 01, 2026 at 01:20:57PM +0200, Louis-Alexis Eyraud wrote:
> In order to prepare the MT8189 SoC support, that requires different
> registers to control PLL status and perform reset BAR, and so a
> different sets of clock operations, split the pll power on and off
> sequences from mtk_pll_prepare/unprepare functions into private
> subfunctions.
> 
> Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@xxxxxxxxxxxxx>

Reviewed-by: Brian Masney <bmasney@xxxxxxxxxx>