Re: [PATCH v8 08/22] RISC-V: Add Sscfg extension CSR definition

[Paul Walmsley]

On Wed, 1 Jul 2026, Atish Patra wrote:

> From: Kaiwen Xue <kaiwenx@xxxxxxxxxxxx>
> 
> This adds the scountinhibit CSR definition and S-mode accessible hpmevent
> bits defined by smcdeleg/ssccfg. scountinhibit allows S-mode to start/stop
> counters directly from S-mode without invoking SBI calls to M-mode. It is
> also used to figure out the counters delegated to S-mode by the M-mode as
> well.
> 
> Signed-off-by: Kaiwen Xue <kaiwenx@xxxxxxxxxxxx>
> Reviewed-by: Clément Léger <cleger@xxxxxxxxxxxx>

Thanks, queued for v7.3 with the typo fixed in the subject line.


- Paul