Re: [PATCH v4 1/4] dt-bindings: timer: Add the Renesas RZ/N1 timer

[Geert Uytterhoeven]

Hi Wolfram,

On Tue, 4 Aug 2026 at 22:06, Wolfram Sang
<wsa+renesas@xxxxxxxxxxxxxxxxxxxx> wrote:
> On Tue, Jul 21, 2026 at 10:29:47AM +0200, Herve Codina (Schneider Electric) wrote:
> > The Renesas RZ/N1 timer block controller is the controller in charge of
> > timers available in the Renesas RZ/N1 SoCs family.
> >
> > This controller handles 8 timers:
> >  - 6 16-bit timers
> >  - 2 32-bit timers
> >
> > Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@xxxxxxxxxxx>
> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxxxxxxxx>
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
>
> In general:
>
> Reviewed-by: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>
>
> One nit:
>
> > +        reg = <0x51001000 0x400>;
>
> Isn't 0x400 a bit excessive? The last documented register in my docs is
> 0x114, so maybe 0x200 will do above?

FTR, 0x200 or 0x400 does not make much of a difference, as this is
mapped in PAGE_SIZE units anyway.

According to Table 2.1 ("Register Map") in the RZ/N1 Introduction
document it could even be 0x1000...

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds