[PATCH v4 07/12] ARM: dts: aspeed: anacapa: Align PDB fan GPIO numbering
From: Colin Huang via B4 Relay
Date: Wed Aug 05 2026 - 09:05:15 EST
From: Rex Fu <rex.fu.amd@xxxxxxxxx>
Update the LPDB and RPDB fan GPIO line names to align with the platform
fan numbering scheme.
The LPDB fan GPIOs are named FAN0 through FAN4, while the RPDB fan GPIOs
are named FAN5 through FAN8. This keeps the GPIO line names consistent
with the fan inventory and platform-level fan numbering.
Signed-off-by: Rex Fu <rex.fu.amd@xxxxxxxxx>
Signed-off-by: Colin Huang <u8813345@xxxxxxxxx>
---
.../aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 33 ++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts
index c7bffa7c6557..ff393ad7cdb7 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts
@@ -8,6 +8,39 @@ / {
compatible = "facebook,anacapa-bmc-evt2", "aspeed,ast2600";
};
+// MB - PDB
+&i2c8 {
+ i2c-mux@72 {
+ i2c8mux0ch0: i2c@0 {
+ gpio@24 {
+ gpio-line-names =
+ "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R",
+ "RPDB_PWRGD_P50V_HSC4_SYS_R",
+ "RPDB_PWRGD_P50V_STBY_SYS_BUF_R",
+ "RPDB_P50V_FAN5_R2_PG", "RPDB_P50V_FAN6_R2_PG",
+ "RPDB_P50V_FAN7_R2_PG", "RPDB_P50V_FAN8_R2_PG",
+ "", "RPDB_FAN5_PRSNT_N_R",
+ "", "RPDB_FAN6_PRSNT_N_R",
+ "RPDB_FAN7_PRSNT_N_R", "RPDB_FAN8_PRSNT_N_R",
+ "", "";
+ };
+ };
+ i2c8mux0ch1: i2c@1 {
+ gpio@24 {
+ gpio-line-names =
+ "LPDB_P50V_FAN0_R2_PG","LPDB_P50V_FAN1_R2_PG",
+ "LPDB_P50V_FAN2_R2_PG","LPDB_P50V_FAN3_R2_PG",
+ "LPDB_P50V_FAN4_R2_PG","LPDB_FAN0_PRSNT_N_R",
+ "LPDB_FAN1_PRSNT_N_R","LPDB_FAN2_PRSNT_N_R",
+ "LPDB_FAN3_PRSNT_N_R","LPDB_FAN4_PRSNT_N_R",
+ "","",
+ "","",
+ "","";
+ };
+ };
+ };
+};
+
// SCM
&i2c9 {
--
2.34.1